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tegra124: clean-ups for DMA driver

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This addresses comments made in the first round of code reviews
for the DMA driver.

BUG=none
BRANCH=none
TEST=built and booted on nyan

Change-Id: I4254b7ce9d6559b6507c074f2493f15179f8f15d
Reviewed-on: https://chromium-review.googlesource.com/173598
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David James <davidjames@chromium.org>
This commit is contained in:
David Hendricks 2013-10-17 12:53:30 -07:00 • committed by chrome-internal-fetch
commit 750c0a5d69
1 changed files with 44 additions and 86 deletions
Download patch file Download diff file Expand all files Collapse all files

130
src/soc/nvidia/tegra124/dma.c
View file

@ -26,41 +26,6 @@
#include "dma.h"
enum {
APB_DMA_CH0 = TEGRA_APB_DMA_BASE + 0x1000,
APB_DMA_CH1 = TEGRA_APB_DMA_BASE + 0x1040,
APB_DMA_CH2 = TEGRA_APB_DMA_BASE + 0x1080,
APB_DMA_CH3 = TEGRA_APB_DMA_BASE + 0x10c0,
APB_DMA_CH4 = TEGRA_APB_DMA_BASE + 0x1100,
APB_DMA_CH5 = TEGRA_APB_DMA_BASE + 0x1140,
APB_DMA_CH6 = TEGRA_APB_DMA_BASE + 0x1180,
APB_DMA_CH7 = TEGRA_APB_DMA_BASE + 0x11c0,
APB_DMA_CH8 = TEGRA_APB_DMA_BASE + 0x1200,
APB_DMA_CH9 = TEGRA_APB_DMA_BASE + 0x1240,
APB_DMA_CH10 = TEGRA_APB_DMA_BASE + 0x1280,
APB_DMA_CH11 = TEGRA_APB_DMA_BASE + 0x12c0,
APB_DMA_CH12 = TEGRA_APB_DMA_BASE + 0x1300,
APB_DMA_CH13 = TEGRA_APB_DMA_BASE + 0x1340,
APB_DMA_CH14 = TEGRA_APB_DMA_BASE + 0x1380,
APB_DMA_CH15 = TEGRA_APB_DMA_BASE + 0x13c0,
APB_DMA_CH16 = TEGRA_APB_DMA_BASE + 0x1400,
APB_DMA_CH17 = TEGRA_APB_DMA_BASE + 0x1440,
APB_DMA_CH18 = TEGRA_APB_DMA_BASE + 0x1480,
APB_DMA_CH19 = TEGRA_APB_DMA_BASE + 0x14c0,
APB_DMA_CH20 = TEGRA_APB_DMA_BASE + 0x1500,
APB_DMA_CH21 = TEGRA_APB_DMA_BASE + 0x1540,
APB_DMA_CH22 = TEGRA_APB_DMA_BASE + 0x1580,
APB_DMA_CH23 = TEGRA_APB_DMA_BASE + 0x15c0,
APB_DMA_CH24 = TEGRA_APB_DMA_BASE + 0x1600,
APB_DMA_CH25 = TEGRA_APB_DMA_BASE + 0x1640,
APB_DMA_CH26 = TEGRA_APB_DMA_BASE + 0x1680,
APB_DMA_CH27 = TEGRA_APB_DMA_BASE + 0x16c0,
APB_DMA_CH28 = TEGRA_APB_DMA_BASE + 0x1700,
APB_DMA_CH29 = TEGRA_APB_DMA_BASE + 0x1740,
APB_DMA_CH30 = TEGRA_APB_DMA_BASE + 0x1780,
APB_DMA_CH31 = TEGRA_APB_DMA_BASE + 0x17c0,
};
/*
* Note: Many APB DMA controller registers are laid out such that each
* bit controls or represents the status for the corresponding channel.
@ -74,7 +39,7 @@ enum {
struct apb_dma {
u32 command; /* 0x00 */
u32 status; /* 0x04 */
u8 rsvd1[0x8];
u32 rsvd1[2];
u32 cntrl_reg; /* 0x10 */
u32 irq_sta_cpu; /* 0x14 */
u32 irq_sta_cop; /* 0x18 */
@ -87,7 +52,7 @@ struct apb_dma {
u32 channel_en_reg; /* 0x34 */
u32 security_reg; /* 0x38 */
u32 channel_swid; /* 0x3c */
u8 rsvd[4];
u32 rsvd[1];
u32 chan_wt_reg0; /* 0x44 */
u32 chan_wt_reg1; /* 0x48 */
u32 chan_wt_reg2; /* 0x4c */
@ -97,8 +62,8 @@ struct apb_dma {
struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE;
/*
* FIXME: Naming in the doc included a superfluous _CHANNEL_n_ for
* each entry which I left out for the sake of conciseness.
* Naming in the doc included a superfluous _CHANNEL_n_ for
* each entry and was left out for the sake of conciseness.
*/
#define APBDMACHAN_CSR_ENB (1 << 31)
#define APBDMACHAN_CSR_IE_EOC (1 << 30)
@ -150,45 +115,41 @@ struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE;
#define APBDMACHAN_WORD_TRANSFER_MASK 0x0fffffff
#define APBDMACHAN_WORD_TRANSFER_SHIFT 2
#define NUM_APB_DMA_CHANNELS 32
#define APB_DMA_CHANNEL(n) \
{ \
.num = n, \
.regs = (struct apb_dma_channel_regs *)APB_DMA_CH##n, \
}
struct apb_dma_channel apb_dma_channels[NUM_APB_DMA_CHANNELS] = {
APB_DMA_CHANNEL(0),
APB_DMA_CHANNEL(1),
APB_DMA_CHANNEL(2),
APB_DMA_CHANNEL(3),
APB_DMA_CHANNEL(4),
APB_DMA_CHANNEL(5),
APB_DMA_CHANNEL(6),
APB_DMA_CHANNEL(7),
APB_DMA_CHANNEL(8),
APB_DMA_CHANNEL(9),
APB_DMA_CHANNEL(10),
APB_DMA_CHANNEL(11),
APB_DMA_CHANNEL(12),
APB_DMA_CHANNEL(13),
APB_DMA_CHANNEL(14),
APB_DMA_CHANNEL(15),
APB_DMA_CHANNEL(16),
APB_DMA_CHANNEL(17),
APB_DMA_CHANNEL(18),
APB_DMA_CHANNEL(19),
APB_DMA_CHANNEL(20),
APB_DMA_CHANNEL(21),
APB_DMA_CHANNEL(22),
APB_DMA_CHANNEL(23),
APB_DMA_CHANNEL(24),
APB_DMA_CHANNEL(25),
APB_DMA_CHANNEL(26),
APB_DMA_CHANNEL(27),
APB_DMA_CHANNEL(28),
APB_DMA_CHANNEL(29),
APB_DMA_CHANNEL(30),
APB_DMA_CHANNEL(31),
#define APB_DMA_OFFSET(n) \
(struct apb_dma_channel_regs *)(TEGRA_APB_DMA_BASE + n)
struct apb_dma_channel apb_dma_channels[] = {
{ .num = 0, .regs = APB_DMA_OFFSET(0x1000) },
{ .num = 1, .regs = APB_DMA_OFFSET(0x1040) },
{ .num = 2, .regs = APB_DMA_OFFSET(0x1080) },
{ .num = 3, .regs = APB_DMA_OFFSET(0x10c0) },
{ .num = 4, .regs = APB_DMA_OFFSET(0x1100) },
{ .num = 5, .regs = APB_DMA_OFFSET(0x1140) },
{ .num = 6, .regs = APB_DMA_OFFSET(0x1180) },
{ .num = 7, .regs = APB_DMA_OFFSET(0x11c0) },
{ .num = 8, .regs = APB_DMA_OFFSET(0x1200) },
{ .num = 9, .regs = APB_DMA_OFFSET(0x1240) },
{ .num = 10, .regs = APB_DMA_OFFSET(0x1280) },
{ .num = 11, .regs = APB_DMA_OFFSET(0x12c0) },
{ .num = 12, .regs = APB_DMA_OFFSET(0x1300) },
{ .num = 13, .regs = APB_DMA_OFFSET(0x1340) },
{ .num = 14, .regs = APB_DMA_OFFSET(0x1380) },
{ .num = 15, .regs = APB_DMA_OFFSET(0x13c0) },
{ .num = 16, .regs = APB_DMA_OFFSET(0x1400) },
{ .num = 17, .regs = APB_DMA_OFFSET(0x1440) },
{ .num = 18, .regs = APB_DMA_OFFSET(0x1480) },
{ .num = 19, .regs = APB_DMA_OFFSET(0x14c0) },
{ .num = 20, .regs = APB_DMA_OFFSET(0x1500) },
{ .num = 21, .regs = APB_DMA_OFFSET(0x1540) },
{ .num = 22, .regs = APB_DMA_OFFSET(0x1580) },
{ .num = 23, .regs = APB_DMA_OFFSET(0x15c0) },
{ .num = 24, .regs = APB_DMA_OFFSET(0x1600) },
{ .num = 25, .regs = APB_DMA_OFFSET(0x1640) },
{ .num = 26, .regs = APB_DMA_OFFSET(0x1680) },
{ .num = 27, .regs = APB_DMA_OFFSET(0x16c0) },
{ .num = 28, .regs = APB_DMA_OFFSET(0x1700) },
{ .num = 29, .regs = APB_DMA_OFFSET(0x1740) },
{ .num = 30, .regs = APB_DMA_OFFSET(0x1780) },
{ .num = 31, .regs = APB_DMA_OFFSET(0x17c0) },
};
int dma_busy(struct apb_dma_channel * const channel)
@ -227,7 +188,7 @@ struct apb_dma_channel * const dma_claim(void)
}
}
if (i == NUM_APB_DMA_CHANNELS)
if (i == ARRAY_SIZE(apb_dma_channels))
return NULL;
apb_dma_channels[i].in_use = 1;
@ -238,8 +199,8 @@ struct apb_dma_channel * const dma_claim(void)
void dma_release(struct apb_dma_channel * const channel)
{
int i;
int dma_in_use = 0;
/* FIXME: make this "thread" friendly */
while (dma_busy(channel))
;
@ -247,14 +208,11 @@ void dma_release(struct apb_dma_channel * const channel)
/* clear the global enable bit if no channels are in use */
for (i = 0; i < ARRAY_SIZE(apb_dma_channels); i++) {
if (apb_dma_channels[i].in_use) {
dma_in_use = 1;
break;
}
if (apb_dma_channels[i].in_use)
return;
}
if (!dma_in_use)
clrbits_le32(&apb_dma->command, APBDMA_COMMAND_GEN);
clrbits_le32(&apb_dma->command, APBDMA_COMMAND_GEN);
}
int dma_start(struct apb_dma_channel * const channel)