broadwell: Expand the PCI device convenience macros
Add defines for PCI device+function for SA/PCH devices and complete the list by adding entries for devices that were missing. Then make use of these defines in pch.c and serialio.c. BUG=chrome-os-partner:28234 TEST=Build and boot on wtm2 Change-Id: Id1b284cfab8a72acf040ea1ce1c38324abccc110 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/199891 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
chrome-internal-fetch
parent
ecebda4eb5
commit
f8c54c70f1
3 changed files with 118 additions and 71 deletions
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@ -20,6 +20,9 @@
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#ifndef _BROADWELL_PCI_DEVS_H_
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#define _BROADWELL_PCI_DEVS_H_
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#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
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#define _PCH_DEVFN(slot,func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
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#if defined(__PRE_RAM__) || defined(__SMM__) || defined(__ROMCC__)
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#include <arch/io.h>
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#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
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@ -27,43 +30,90 @@
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#else
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#include <device/device.h>
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#include <device/pci_def.h>
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#define _SA_DEV(slot) dev_find_slot(0, \
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PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0))
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#define _PCH_DEV(slot,func) dev_find_slot(0, \
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PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func))
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#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot))
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#define _PCH_DEV(slot,func) dev_find_slot(0, _PCH_DEVFN(slot, func))
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#endif
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/* System Agent Devices */
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#define SA_DEV_SLOT_ROOT 0x00
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#define SA_DEV_SLOT_IGD 0x02
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#define SA_DEV_SLOT_MINIHD 0x03
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#define SA_DEVFN_ROOT _SA_DEVFN(ROOT)
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#define SA_DEV_ROOT _SA_DEV(ROOT)
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#define SA_DEV_ROOT _SA_DEV(ROOT)
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#define SA_DEV_IGD _SA_DEV(IGD)
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#define SA_DEV_MINIHD _SA_DEV(MINIHD)
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#define SA_DEV_SLOT_IGD 0x02
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#define SA_DEVFN_IGD _SA_DEVFN(IGD)
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#define SA_DEV_IGD _SA_DEV(IGD)
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#define SA_DEV_SLOT_MINIHD 0x03
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#define SA_DEVFN_MINIHD _SA_DEVFN(MINIHD)
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#define SA_DEV_MINIHD _SA_DEV(MINIHD)
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/* PCH Devices */
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#define PCH_DEV_SLOT_XHCI 0x14
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#define PCH_DEV_SLOT_SIO 0x15
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#define PCH_DEV_SLOT_ME 0x16
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#define PCH_DEV_SLOT_HDA 0x1b
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#define PCH_DEV_SLOT_PCIE 0x1c
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#define PCH_DEV_SLOT_EHCI 0x1d
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#define PCH_DEV_SLOT_LPC 0x1f
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#define PCH_DEV_SLOT_ADSP 0x13
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#define PCH_DEVFN_ADSP _PCH_DEVFN(ADSP, 0)
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#define PCH_DEV_ADSP _PCH_DEV(ADSP, 0)
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#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0)
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#define PCH_DEV_UART0 _PCH_DEV(UART0, 0)
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#define PCH_DEV_UART1 _PCH_DEV(UART1, 0)
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#define PCH_DEV_ME _PCH_DEV(ME, 0)
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#define PCH_DEV_HDA _PCH_DEV(HDA, 0)
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#define PCH_DEV_EHCI _PCH_DEV(EHCI, 0)
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#define PCH_DEV_LPC _PCH_DEV(LPC, 0)
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#define PCH_DEV_IDE _PCH_DEV(LPC, 1)
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#define PCH_DEV_SATA _PCH_DEV(LPC, 2)
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#define PCH_DEV_SMBUS _PCH_DEV(LPC, 3)
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#define PCH_DEV_SATA2 _PCH_DEV(LPC, 5)
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#define PCH_DEV_THERMAL _PCH_DEV(LPC, 6)
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#define PCH_DEV_SLOT_XHCI 0x14
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#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0)
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#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0)
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#define PCH_DEV_SLOT_SIO 0x15
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#define PCH_DEV_SDMA _PCH_DEV(SIO, 0)
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#define PCH_DEV_I2C0 _PCH_DEV(SIO, 1)
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#define PCH_DEV_I2C1 _PCH_DEV(SIO, 2)
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#define PCH_DEV_SPI0 _PCH_DEV(SIO, 3)
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#define PCH_DEV_SPI1 _PCH_DEV(SIO, 4)
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#define PCH_DEV_UART0 _PCH_DEV(SIO, 5)
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#define PCH_DEV_UART1 _PCH_DEV(SIO, 6)
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#define PCH_DEVFN_SDMA _PCH_DEVFN(SIO, 0)
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#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO, 1)
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#define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO, 2)
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#define PCH_DEVFN_SPI0 _PCH_DEVFN(SIO, 3)
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#define PCH_DEVFN_SPI1 _PCH_DEVFN(SIO, 4)
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#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO, 5)
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#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO, 6)
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#define PCH_DEV_SLOT_ME 0x16
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#define PCH_DEVFN_ME _PCH_DEVFN(ME, 0)
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#define PCH_DEVFN_ME_2 _PCH_DEVFN(ME, 1)
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#define PCH_DEVFN_ME_IDER _PCH_DEVFN(ME, 2)
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#define PCH_DEVFN_ME_KT _PCH_DEVFN(ME, 3)
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#define PCH_DEV_ME _PCH_DEV(ME, 0)
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#define PCH_DEV_ME_2 _PCH_DEV(ME, 1)
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#define PCH_DEV_ME_IDER _PCH_DEV(ME, 2)
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#define PCH_DEV_ME_KT _PCH_DEV(ME, 3)
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#define PCH_DEV_SLOT_SDIO 0x17
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#define PCH_DEVFN_SDIO _PCH_DEVFN(SDIO, 0)
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#define PCH_DEV_SDIO _PCH_DEV(SDIO, 0)
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#define PCH_DEV_SLOT_GBE 0x19
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#define PCH_DEVFN_GBE _PCH_DEVFN(GBE, 0)
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#define PCH_DEV_GBE _PCH_DEV(GBE, 0)
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#define PCH_DEV_SLOT_HDA 0x1b
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#define PCH_DEVFN_HDA _PCH_DEVFN(HDA, 0)
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#define PCH_DEV_HDA _PCH_DEV(HDA, 0)
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#define PCH_DEV_SLOT_PCIE 0x1c
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#define PCH_DEV_SLOT_EHCI 0x1d
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#define PCH_DEVFN_EHCI _PCH_DEVFN(EHCI, 0)
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#define PCH_DEV_EHCI _PCH_DEV(EHCI, 0)
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#define PCH_DEV_SLOT_LPC 0x1f
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#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0)
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#define PCH_DEVFN_IDE _PCH_DEVFN(LPC, 1)
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#define PCH_DEVFN_SATA _PCH_DEVFN(LPC, 2)
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#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 3)
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#define PCH_DEVFN_SATA2 _PCH_DEVFN(LPC, 5)
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#define PCH_DEVFN_THERMAL _PCH_DEVFN(LPC, 6)
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#define PCH_DEV_LPC _PCH_DEV(LPC, 0)
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#define PCH_DEV_IDE _PCH_DEV(LPC, 1)
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#define PCH_DEV_SATA _PCH_DEV(LPC, 2)
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#define PCH_DEV_SMBUS _PCH_DEV(LPC, 3)
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#define PCH_DEV_SATA2 _PCH_DEV(LPC, 5)
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#define PCH_DEV_THERMAL _PCH_DEV(LPC, 6)
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#endif
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@ -92,91 +92,88 @@ static void pch_enable_d3hot(device_t dev)
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void pch_disable_devfn(device_t dev)
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{
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switch (dev->path.pci.devfn) {
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case PCI_DEVFN(19, 0): /* Audio DSP */
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case PCH_DEVFN_ADSP: /* Audio DSP */
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RCBA32_OR(FD, PCH_DISABLE_ADSPD);
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break;
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case PCI_DEVFN(20, 0): /* XHCI */
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case PCH_DEVFN_XHCI: /* XHCI */
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RCBA32_OR(FD, PCH_DISABLE_XHCI);
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break;
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case PCI_DEVFN(21, 0): /* DMA */
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case PCH_DEVFN_SDMA: /* DMA */
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pch_enable_d3hot(dev);
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pch_iobp_update(SIO_IOBP_FUNCDIS0, ~0UL, SIO_IOBP_FUNCDIS_DIS);
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break;
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case PCI_DEVFN(21, 1): /* I2C0 */
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case PCH_DEVFN_I2C0: /* I2C0 */
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pch_enable_d3hot(dev);
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pch_iobp_update(SIO_IOBP_FUNCDIS1, ~0UL, SIO_IOBP_FUNCDIS_DIS);
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break;
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case PCI_DEVFN(21, 2): /* I2C1 */
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case PCH_DEVFN_I2C1: /* I2C1 */
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pch_enable_d3hot(dev);
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pch_iobp_update(SIO_IOBP_FUNCDIS2, ~0UL, SIO_IOBP_FUNCDIS_DIS);
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break;
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case PCI_DEVFN(21, 3): /* SPI0 */
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case PCH_DEVFN_SPI0: /* SPI0 */
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pch_enable_d3hot(dev);
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pch_iobp_update(SIO_IOBP_FUNCDIS3, ~0UL, SIO_IOBP_FUNCDIS_DIS);
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break;
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case PCI_DEVFN(21, 4): /* SPI1 */
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case PCH_DEVFN_SPI1: /* SPI1 */
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pch_enable_d3hot(dev);
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pch_iobp_update(SIO_IOBP_FUNCDIS4, ~0UL, SIO_IOBP_FUNCDIS_DIS);
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break;
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case PCI_DEVFN(21, 5): /* UART0 */
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case PCH_DEVFN_UART0: /* UART0 */
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pch_enable_d3hot(dev);
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pch_iobp_update(SIO_IOBP_FUNCDIS5, ~0UL, SIO_IOBP_FUNCDIS_DIS);
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break;
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case PCI_DEVFN(21, 6): /* UART1 */
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case PCH_DEVFN_UART1: /* UART1 */
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pch_enable_d3hot(dev);
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pch_iobp_update(SIO_IOBP_FUNCDIS6, ~0UL, SIO_IOBP_FUNCDIS_DIS);
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break;
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case PCI_DEVFN(22, 0): /* MEI #1 */
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case PCH_DEVFN_ME: /* MEI #1 */
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RCBA32_OR(FD2, PCH_DISABLE_MEI1);
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break;
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case PCI_DEVFN(22, 1): /* MEI #2 */
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case PCH_DEVFN_ME_2: /* MEI #2 */
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RCBA32_OR(FD2, PCH_DISABLE_MEI2);
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break;
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case PCI_DEVFN(22, 2): /* IDE-R */
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case PCH_DEVFN_ME_IDER: /* IDE-R */
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RCBA32_OR(FD2, PCH_DISABLE_IDER);
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break;
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case PCI_DEVFN(22, 3): /* KT */
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case PCH_DEVFN_ME_KT: /* KT */
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RCBA32_OR(FD2, PCH_DISABLE_KT);
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break;
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case PCI_DEVFN(23, 0): /* SDIO */
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case PCH_DEVFN_SDIO: /* SDIO */
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pch_enable_d3hot(dev);
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pch_iobp_update(SIO_IOBP_FUNCDIS7, ~0UL, SIO_IOBP_FUNCDIS_DIS);
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break;
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case PCI_DEVFN(25, 0): /* Gigabit Ethernet */
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case PCH_DEVFN_GBE: /* Gigabit Ethernet */
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RCBA32_OR(BUC, PCH_DISABLE_GBE);
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break;
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case PCI_DEVFN(26, 0): /* EHCI #2 */
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RCBA32_OR(FD, PCH_DISABLE_EHCI2);
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break;
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case PCI_DEVFN(27, 0): /* HD Audio Controller */
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case PCH_DEVFN_HDA: /* HD Audio Controller */
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RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO);
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break;
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case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */
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case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */
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case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */
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case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */
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case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */
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case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */
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case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */
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case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */
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case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 0): /* PCI Express Root Port 1 */
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case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 1): /* PCI Express Root Port 2 */
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case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 2): /* PCI Express Root Port 3 */
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case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 3): /* PCI Express Root Port 4 */
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case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 4): /* PCI Express Root Port 5 */
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case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 5): /* PCI Express Root Port 6 */
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case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 6): /* PCI Express Root Port 7 */
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case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 7): /* PCI Express Root Port 8 */
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RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(dev->path.pci.devfn)));
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break;
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case PCI_DEVFN(29, 0): /* EHCI #1 */
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case PCH_DEVFN_EHCI: /* EHCI #1 */
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RCBA32_OR(FD, PCH_DISABLE_EHCI1);
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break;
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case PCI_DEVFN(31, 0): /* LPC */
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case PCH_DEVFN_LPC: /* LPC */
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RCBA32_OR(FD, PCH_DISABLE_LPC);
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break;
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case PCI_DEVFN(31, 2): /* SATA #1 */
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case PCH_DEVFN_SATA: /* SATA #1 */
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RCBA32_OR(FD, PCH_DISABLE_SATA1);
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break;
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case PCI_DEVFN(31, 3): /* SMBUS */
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case PCH_DEVFN_SMBUS: /* SMBUS */
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RCBA32_OR(FD, PCH_DISABLE_SMBUS);
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break;
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case PCI_DEVFN(31, 5): /* SATA #2 */
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case PCH_DEVFN_SATA2: /* SATA #2 */
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RCBA32_OR(FD, PCH_DISABLE_SATA2);
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break;
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case PCI_DEVFN(31, 6): /* Thermal Subsystem */
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case PCH_DEVFN_THERMAL: /* Thermal Subsystem */
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RCBA32_OR(FD, PCH_DISABLE_THERMAL);
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break;
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}
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@ -186,13 +183,12 @@ void broadwell_pch_enable_dev(device_t dev)
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{
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u32 reg32;
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/* PCH PCIe Root Ports are handled in PCIe driver. */
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if (PCI_SLOT(dev->path.pci.devfn) == PCH_DEV_SLOT_PCIE)
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return;
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/* EHCI disable is handled in ramstage driver */
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if (PCI_SLOT(dev->path.pci.devfn) == PCH_DEV_SLOT_EHCI)
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/* These devices need special enable/disable handling */
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switch (PCI_SLOT(dev->path.pci.devfn)) {
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case PCH_DEV_SLOT_PCIE:
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case PCH_DEV_SLOT_EHCI:
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return;
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}
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if (!dev->enabled) {
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printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
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@ -27,6 +27,7 @@
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#include <stdlib.h>
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#include <broadwell/iobp.h>
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#include <broadwell/nvs.h>
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#include <broadwell/pci_devs.h>
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#include <broadwell/pch.h>
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#include <broadwell/ramstage.h>
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#include <broadwell/rcba.h>
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@ -45,9 +46,9 @@ static int serialio_uart_is_debug(struct device *dev)
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{
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#if CONFIG_INTEL_PCH_UART_CONSOLE
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switch (dev->path.pci.devfn) {
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case PCI_DEVFN(21, 5): /* UART0 */
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case PCH_DEVFN_UART0: /* UART0 */
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return !!(CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 0);
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case PCI_DEVFN(21, 6): /* UART1 */
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case PCH_DEVFN_UART1: /* UART1 */
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return !!(CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 1);
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}
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#endif
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@ -195,57 +196,57 @@ static void serialio_init(struct device *dev)
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if (!config->sio_acpi_mode)
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serialio_enable_clock(bar0);
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else if (dev->path.pci.devfn != PCI_DEVFN(21, 0))
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else if (dev->path.pci.devfn != PCH_DEVFN_SDMA)
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serialio_enable_d3hot(dev); /* all but SDMA */
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switch (dev->path.pci.devfn) {
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case PCI_DEVFN(21, 0): /* SDMA */
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case PCH_DEVFN_SDMA: /* SDMA */
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sio_index = SIO_ID_SDMA;
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serialio_init_once(config->sio_acpi_mode);
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serialio_d21_mode(sio_index, SIO_PIN_INTB,
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config->sio_acpi_mode);
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break;
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case PCI_DEVFN(21, 1): /* I2C0 */
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case PCH_DEVFN_I2C0: /* I2C0 */
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sio_index = SIO_ID_I2C0;
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serialio_d21_ltr(bar0);
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serialio_i2c_voltage_sel(bar0, config->sio_i2c0_voltage);
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serialio_d21_mode(sio_index, SIO_PIN_INTC,
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config->sio_acpi_mode);
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break;
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case PCI_DEVFN(21, 2): /* I2C1 */
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case PCH_DEVFN_I2C1: /* I2C1 */
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sio_index = SIO_ID_I2C1;
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serialio_d21_ltr(bar0);
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serialio_i2c_voltage_sel(bar0, config->sio_i2c1_voltage);
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serialio_d21_mode(sio_index, SIO_PIN_INTC,
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config->sio_acpi_mode);
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break;
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case PCI_DEVFN(21, 3): /* SPI0 */
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case PCH_DEVFN_SPI0: /* SPI0 */
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sio_index = SIO_ID_SPI0;
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serialio_d21_ltr(bar0);
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serialio_d21_mode(sio_index, SIO_PIN_INTC,
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config->sio_acpi_mode);
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break;
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case PCI_DEVFN(21, 4): /* SPI1 */
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case PCH_DEVFN_SPI1: /* SPI1 */
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sio_index = SIO_ID_SPI1;
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serialio_d21_ltr(bar0);
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serialio_d21_mode(sio_index, SIO_PIN_INTC,
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config->sio_acpi_mode);
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break;
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case PCI_DEVFN(21, 5): /* UART0 */
|
||||
case PCH_DEVFN_UART0: /* UART0 */
|
||||
sio_index = SIO_ID_UART0;
|
||||
if (!serialio_uart_is_debug(dev))
|
||||
serialio_d21_ltr(bar0);
|
||||
serialio_d21_mode(sio_index, SIO_PIN_INTD,
|
||||
config->sio_acpi_mode);
|
||||
break;
|
||||
case PCI_DEVFN(21, 6): /* UART1 */
|
||||
case PCH_DEVFN_UART1: /* UART1 */
|
||||
sio_index = SIO_ID_UART1;
|
||||
if (!serialio_uart_is_debug(dev))
|
||||
serialio_d21_ltr(bar0);
|
||||
serialio_d21_mode(sio_index, SIO_PIN_INTD,
|
||||
config->sio_acpi_mode);
|
||||
break;
|
||||
case PCI_DEVFN(23, 0): /* SDIO */
|
||||
case PCH_DEVFN_SDIO: /* SDIO */
|
||||
sio_index = SIO_ID_SDIO;
|
||||
serialio_d23_ltr(bar0);
|
||||
serialio_d23_mode(config->sio_acpi_mode);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue