baytrail: allow configuration of io hole size
The updated MRC wrapper allow the IO hole size to be configured from the coreboot side of things. BUG=None BRANCH=baytrail CQ-DEPEND=CL:*152595 TEST=Built and booted. Also changed io hole size from mainboard as test. Change-Id: I7a626764aecce94bbaf35d884606480f22a9aa84 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/183269 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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2 changed files with 7 additions and 1 deletions
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@ -28,7 +28,7 @@
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#ifndef _MRC_WRAPPER_H_
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#define _MRC_WRAPPER_H_
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#define MRC_PARAMS_VER 2
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#define MRC_PARAMS_VER 3
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#define NUM_CHANNELS 2
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@ -79,6 +79,7 @@ struct mrc_params {
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int txe_size_mb; /* TXE memory size in megabytes. */
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int rmt_enabled; /* Enable RMT training + prints. */
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int io_hole_mb; /* Size of IO hole in MiB. */
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/* Outputs */
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void *txe_base_address;
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@ -128,6 +128,11 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
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#if CONFIG_MRC_RMT
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mp->rmt_enabled = 1;
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#endif
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/* Default to 2GiB IO hole. */
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if (!mp->io_hole_mb)
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mp->io_hole_mb = 2048;
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if (recovery_mode_enabled()) {
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printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n");
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} else if (!mrc_cache_get_current(&cache)) {
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