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broadwell: pmutil: Add new acpi_sci_irq() function

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This function will read the chipset register to determine the
interrupt assigned for SCI in order to create the ACPI MADT
IRQ override entry.

BUG=chrome-os-partner:28234
TEST=None

Change-Id: Idba2ab3d84fa843304d03b3e707c3678ed16e71e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199186
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2014-05-01 13:53:49 -07:00 • committed by chrome-internal-fetch
commit 80ad8bb9bd
1 changed files with 28 additions and 0 deletions
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28
src/soc/intel/broadwell/pmutil.c
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@ -422,3 +422,31 @@ void disable_gpe(u32 mask)
gpe0_en &= ~mask;
outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));
}
int acpi_sci_irq(void)
{
int scis = pci_read_config32(PCH_DEV_LPC, ACPI_CNTL) & SCI_IRQ_SEL;
int sci_irq = 9;
/* Determine how SCI is routed. */
switch (scis) {
case SCIS_IRQ9:
case SCIS_IRQ10:
case SCIS_IRQ11:
sci_irq = scis - SCIS_IRQ9 + 9;
break;
case SCIS_IRQ20:
case SCIS_IRQ21:
case SCIS_IRQ22:
case SCIS_IRQ23:
sci_irq = scis - SCIS_IRQ20 + 20;
break;
default:
printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n");
sci_irq = 9;
break;
}
printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq);
return sci_irq;
}