tegra124: add clock support code for graphics.
Add a graphics_clock function which is where we intend to do all clock
graphics init. This is modeled on how we are doing the UART clock; keep
it all in one place, not spread everywhere. Add sor_clock_{start,stop}
functions. We must start and stop the SOR clocks beore we mess with the
plldp.
BUG=None
TEST=This code builds and boots and shows graphics and depth charge screen.
BRANCH=None
Change-Id: Ida4a73f9020e5542f16d2ab0793fb2116156d562
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/175162
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
This commit is contained in:
Ronald G. Minnich
chrome-internal-fetch
parent
df4c515d73
commit
b8eb6ab4cd
3 changed files with 63 additions and 25 deletions
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@ -79,7 +79,8 @@ union __attribute__((transparent_union)) pll_fields {
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/* This table defines the frequency dividers for every PLL to turn the external
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* OSC clock into the frequencies defined by TEGRA_PLL*_KHZ in soc/clock.h.
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* All PLLs have three dividers (N, M and P), with the governing formula for
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* the output frequency being OUT = (IN / m) * N / (2^P). */
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* the output frequency being OUT = (IN / m) * N / (2^P).
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* Yes, it really is one equation with three unknowns ... */
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struct {
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int khz;
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struct pllcx_dividers pllx; /* target: 1900 MHz */
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@ -87,6 +88,7 @@ struct {
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struct pllcx_dividers pllc; /* target: 600 MHz */
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struct pllpad_dividers plld; /* target: 925 MHz */
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struct pllu_dividers pllu; /* target; 960 MHz */
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struct pllcx_dividers plldp; /* target; 270 MHz */
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} static const osc_table[16] = {
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[OSC_FREQ_OSC12]{
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.khz = 12000,
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@ -95,6 +97,7 @@ struct {
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.pllc = {.n = 50, .m = 1, .p = 0},
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.plld = {.n = 925, .m = 12, .p = 0, .cpcon = 12},
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.pllu = {.n = 80, .m = 1, .p = 0, .cpcon = 3},
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.plldp = {.n = 90, .m = 1, .p = 3}, /* 270 MHz */
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},
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[OSC_FREQ_OSC13]{
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.khz = 13000,
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@ -103,6 +106,7 @@ struct {
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.pllc = {.n = 231, .m = 5, .p = 0}, /* 600.6 MHz */
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.plld = {.n = 925, .m = 13, .p = 0, .cpcon = 12},
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.pllu = {.n = 960, .m = 13, .p = 0, .cpcon = 12},
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.plldp = {.n = 83, .m = 1, .p = 3}, /* 269.75 MHz */
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},
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[OSC_FREQ_OSC16P8]{
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.khz = 16800,
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@ -111,6 +115,7 @@ struct {
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.pllc = {.n = 250, .m = 7, .p = 0},
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.plld = {.n = 936, .m = 17, .p = 0, .cpcon = 12},/* 924.9 MHz */
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.pllu = {.n = 400, .m = 7, .p = 0, .cpcon = 8},
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.plldp = {.n = 67, .m = 1, .p = 3}, /* 268 MHz */
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},
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[OSC_FREQ_OSC19P2]{
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.khz = 19200,
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@ -119,6 +124,7 @@ struct {
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.pllc = {.n = 125, .m = 4, .p = 0},
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.plld = {.n = 819, .m = 17, .p = 0, .cpcon = 12},/* 924.9 MHz */
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.pllu = {.n = 50, .m = 1, .p = 0, .cpcon = 2},
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.plldp = {.n = 57, .m = 1, .p = 3}, /* 270.75 MHz */
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},
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[OSC_FREQ_OSC26]{
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.khz = 26000,
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@ -127,6 +133,7 @@ struct {
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.pllc = {.n = 23, .m = 1, .p = 0}, /* 598 MHz */
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.plld = {.n = 925, .m = 26, .p = 0, .cpcon = 12},
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.pllu = {.n = 480, .m = 13, .p = 0, .cpcon = 8},
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.plldp = {.n = 41, .m = 1, .p = 3}, /* 266.50 MHz */
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},
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[OSC_FREQ_OSC38P4]{
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.khz = 38400,
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@ -135,6 +142,7 @@ struct {
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.pllc = {.n = 125, .m = 4, .p = 0},
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.plld = {.n = 819, .m = 17, .p = 0, .cpcon = 12},/* 924.9 MHz */
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.pllu = {.n = 50, .m = 1, .p = 0, .cpcon = 2},
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.plldp = {.n = 28, .m = 1, .p = 3}, /* 266 MHz */
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},
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[OSC_FREQ_OSC48]{
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.khz = 48000,
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@ -143,6 +151,7 @@ struct {
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.pllc = {.n = 50, .m = 1, .p = 0},
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.plld = {.n = 925, .m = 12, .p = 0, .cpcon = 12},
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.pllu = {.n = 80, .m = 1, .p = 0, .cpcon = 3},
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.plldp = {.n = 22, .m = 1, .p = 3}, /* 264 MHz */
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},
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};
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@ -189,6 +198,23 @@ static void adjust_pllp_out_freqs(void)
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writel(reg, &clk_rst->pllp_outb);
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}
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#define SOR0_CLK_SEL0 (1 << 14)
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#define SOR0_CLK_SEL1 (1 << 15)
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void sor_clock_stop(void)
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{
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/* The Serial Output Resource clock has to be off
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* before we start the plldp. Learned the hard way.
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* FIXME: this has to be cleaned up a bit more.
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* Waiting on some new info from Nvidia.
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*/
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clrbits_le32(&clk_rst->clk_src_sor, SOR0_CLK_SEL0 | SOR0_CLK_SEL1);
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}
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void sor_clock_start(void)
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{
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setbits_le32(&clk_rst->clk_src_sor, SOR0_CLK_SEL0 | SOR0_CLK_SEL1);
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}
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static void init_pll(u32 *base, u32 *misc, const union pll_fields pll)
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{
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u32 dividers = pll.div.n << PLL_BASE_DIVN_SHIFT |
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@ -197,7 +223,6 @@ static void init_pll(u32 *base, u32 *misc, const union pll_fields pll)
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/* Write dividers but BYPASS the PLL while we're messing with it. */
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writel(dividers | PLL_BASE_BYPASS, base);
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/* Set CPCON field (defaults to 0 if it doesn't exist for this PLL) */
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writel(pll.div.cpcon << PLL_MISC_CPCON_SHIFT, misc);
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@ -237,6 +262,32 @@ static void init_utmip_pll(void)
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setbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */
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}
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/* Graphics just has to be different. There's a few more bits we
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* need to set in here, but it makes sense just to restrict all the
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* special bits to this one function.
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*/
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void graphics_clock(void)
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{
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int osc = clock_get_osc_bits();
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u32 *cfg = &clk_rst->plldp_ss_cfg;
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/* the vendor code sets the dither bit (28)
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* an undocumented bit (24)
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* and clamp while we mess with it (22)
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* Dither is pretty important to display port
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* so we really do need to handle these bits.
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* I'm not willing to not clamp it, even if
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* it might "mostly work" with it not set,
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* I don't want to find out in a few months
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* that it is needed.
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*/
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u32 scfg = (1<<28) | (1<<24) | (1<<22);
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writel(scfg, cfg);
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init_pll(&clk_rst->plldp_base, &clk_rst->plldp_misc, osc_table[osc].plldp);
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/* leave dither and undoc bits set, release clamp */
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scfg = (1<<28) | (1<<24);
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writel(scfg, cfg);
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}
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/* Initialize the UART and put it on CLK_M so we can use it during clock_init().
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* Will later move it to PLLP in clock_config(). The divisor must be very small
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* to accomodate 12KHz OSCs, so we override the 16.0 UART divider with the 15.1
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@ -647,7 +647,7 @@ void dp_io_powerup(void)
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// struct clk_rst_ctlr *clkrst =
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// (struct clk_rst_ctlr *)TEGRA_CLK_RST_BASE;
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u32 reg_val;
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printk(BIOS_SPEW, "%s: entry\n", __func__);
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@ -655,26 +655,8 @@ void dp_io_powerup(void)
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printk(BIOS_SPEW, "JZ: %s: %d: do nothing, ret\n", __func__, __LINE__);
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return;
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#endif
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#define SOR0_CLK_SEL0 (1 << 14)
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#define SOR0_CLK_SEL1 (1 << 15)
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// REG(CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0, SOR0_CLK_SEL1, 0);
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// REG(CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0, SOR0_CLK_SEL0, 0);//sor safe clock
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reg_val = READL((void *)(0x60006000 + 0x414));
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reg_val &= ~(SOR0_CLK_SEL0 | SOR0_CLK_SEL1);
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WRITEL(reg_val, (void *)(0x60006000 + 0x414));
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// clock(PLLDP, 270)
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WRITEL(0, (void *)(0x60006000 + 0x594)); // plldp_misc
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WRITEL(0x11400000, (void *)(0x60006000 + 0x598)); // plldp_ss_cfg
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WRITEL(0x80305a01, (void *)(0x60006000 + 0x590));// plldp_base, 12 * 90 / 4 = 270
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WRITEL(0x11400000, (void *)(0x60006000 + 0x598)); // plldp_ss_cfg
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WRITEL(0x40000000, (void *)(0x60006000 + 0x594)); // misc: enable lock
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WRITEL(0xc0305a01, (void *)(0x60006000 + 0x590)); // base: enable
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WRITEL(0xd8305a01, (void *)(0x60006000 + 0x590)); // base: check lock
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WRITEL(0x58305a01, (void *)(0x60006000 + 0x590)); // base: disable bypass
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WRITEL(0x11000000, (void *)(0x60006000 + 0x598)); // release clamp
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udelay(10); // wait for plldp ready
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sor_clock_stop();
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graphics_clock();
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SOR_WRITE(SOR_NV_PDISP_SOR_CLK_CNTRL_0, (6 << 2) | 2);//select PLLDP, lowest speed(6x)
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SOR_WRITE(SOR_NV_PDISP_SOR_DP_PADCTL0_0, 0x00800000); //set PDCAL
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@ -888,11 +870,12 @@ void dp_link_training(u32 lanes, u32 speed)
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SOR_WRITE(SOR_NV_PDISP_SOR_CLK_CNTRL_0, ((speed << 2) | 2));
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udelay(100);
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//REG(CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0,SOR0_CLK_SEL0, 1) //sor clk=pad macro output
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sor_clock_start();
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#if 0
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reg_val = readl((void *)(0x60006000 + 0x414));
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reg_val |= SOR0_CLK_SEL0;
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writel(reg_val, (void *)(0x60006000 + 0x414));
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#endif
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SOR_WRITE(SOR_NV_PDISP_SOR_DP_LINKCTL0_0,
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(((0xF >> (4 - lanes)) << 16) | 1));
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@ -239,5 +239,9 @@ void clock_cpu0_config_and_reset(void * entry);
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void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x);
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void clock_init(void);
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void clock_init_arm_generic_timer(void);
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void sor_clock_stop(void);
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void sor_clock_start(void);
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void graphics_clock(void);
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#endif /* __SOC_NVIDIA_TEGRA124_CLOCK_H__ */
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