baytrail: DPTF: Enable mainboard-specific PPCC

Allow PL1 to be set at the mainboard level.

BUG=chrome-os-partner:26436
TEST=Run DPTF utility, verify specified PL1 settings are still in place.
Modify PL1 settings at mainboard level, verify that changes are
reflected in DPTF utility.
BRANCH=Rambi.

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Id05701385867420e4d0f129f38dda0d3580abaff
Reviewed-on: https://chromium-review.googlesource.com/189576
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

src/mainboard/google/rambi/acpi/dptf.asl

@@ -49,5 +49,26 @@ Name (DTRT, Package () {
 	Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
 })
 
+Name (MPPC, Package ()
+{
+	0x2,		// Revision
+	Package () {	// Power Limit 1
+		0,	// PowerLimitIndex, 0 for Power Limit 1
+		1600,	// PowerLimitMinimum
+		6200,	// PowerLimitMaximum
+		1000,	// TimeWindowMinimum
+		1000,	// TimeWindowMaximum
+		200	// StepSize
+	},
+	Package () {	// Power Limit 2
+		1,	// PowerLimitIndex, 1 for Power Limit 2
+		8000,	// PowerLimitMinimum
+		8000,	// PowerLimitMaximum
+		1000,	// TimeWindowMinimum
+		1000,	// TimeWindowMaximum
+		1000	// StepSize
+	}
+})
+
 /* Include Baytrail DPTF */
 #include <soc/intel/baytrail/acpi/dptf/dptf.asl>

src/soc/intel/baytrail/acpi/dptf/cpu.asl

@@ -127,26 +127,11 @@ Device (TCPU)
 		}
 	}
 
-	Name (PPCC, Package ()
+	/* Return PPCC table defined by mainboard */
+	Method (PPCC)
 	{
-		0x2,		// Revision
-		Package () {	// Power Limit 1
-			0,	// PowerLimitIndex, 0 for Power Limit 1
-			1600,	// PowerLimitMinimum
-			6200,	// PowerLimitMaximum
-			1000,	// TimeWindowMinimum
-			1000,	// TimeWindowMaximum
-			200	// StepSize
-		},
-		Package () {	// Power Limit 2
-			1,	// PowerLimitIndex, 1 for Power Limit 2
-			8000,	// PowerLimitMinimum
-			8000,	// PowerLimitMaximum
-			1000,	// TimeWindowMinimum
-			1000,	// TimeWindowMaximum
-			1000	// StepSize
-		}
-	})
+		Return (\_SB.MPPC)
+	}
 
 #ifdef DPTF_CPU_CRITICAL
 	Method (_CRT)