broadwell: cpu.h: Split MSR defines to separate header
Create a new header at broadwell/msr.h that contains the various defined MSRs for this CPU generation. The MSRs from cpu.h and the ones defined in smmrelocate.c are in this new header. BUG=chrome-os-partner:28234 TEST=None Change-Id: Id0652d0f7e4bad0992c057b530fc5e05e2dfabb2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198739 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
chrome-internal-fetch
parent
2a25950670
commit
01148cd2c9
4 changed files with 113 additions and 93 deletions
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@ -37,81 +37,6 @@
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/* Haswell bus clock is fixed at 100MHz */
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#define HASWELL_BCLK 100
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#define CORE_THREAD_COUNT_MSR 0x35
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#define IA32_FEATURE_CONTROL 0x3a
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#define CPUID_VMX (1 << 5)
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#define CPUID_SMX (1 << 6)
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#define MSR_FEATURE_CONFIG 0x13c
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#define MSR_FLEX_RATIO 0x194
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#define FLEX_RATIO_LOCK (1 << 20)
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#define FLEX_RATIO_EN (1 << 16)
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#define IA32_PLATFORM_DCA_CAP 0x1f8
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#define IA32_MISC_ENABLE 0x1a0
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#define MSR_TEMPERATURE_TARGET 0x1a2
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#define IA32_PERF_CTL 0x199
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#define IA32_THERM_INTERRUPT 0x19b
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#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
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#define ENERGY_POLICY_PERFORMANCE 0
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#define ENERGY_POLICY_NORMAL 6
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#define ENERGY_POLICY_POWERSAVE 15
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#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
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#define MSR_LT_LOCK_MEMORY 0x2e7
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#define IA32_MC0_STATUS 0x401
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#define MSR_PIC_MSG_CONTROL 0x2e
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#define MSR_PLATFORM_INFO 0xce
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#define PLATFORM_INFO_SET_TDP (1 << 29)
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#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
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#define MSR_PMG_IO_CAPTURE_BASE 0xe4
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#define MSR_MISC_PWR_MGMT 0x1aa
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#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
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#define MSR_TURBO_RATIO_LIMIT 0x1ad
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#define MSR_POWER_CTL 0x1fc
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#define MSR_C_STATE_LATENCY_CONTROL_0 0x60a
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#define MSR_C_STATE_LATENCY_CONTROL_1 0x60b
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#define MSR_C_STATE_LATENCY_CONTROL_2 0x60c
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#define MSR_C_STATE_LATENCY_CONTROL_3 0x633
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#define MSR_C_STATE_LATENCY_CONTROL_4 0x634
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#define MSR_C_STATE_LATENCY_CONTROL_5 0x635
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#define IRTL_VALID (1 << 15)
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#define IRTL_1_NS (0 << 10)
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#define IRTL_32_NS (1 << 10)
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#define IRTL_1024_NS (2 << 10)
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#define IRTL_32768_NS (3 << 10)
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#define IRTL_1048576_NS (4 << 10)
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#define IRTL_33554432_NS (5 << 10)
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#define IRTL_RESPONSE_MASK (0x3ff)
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/* long duration in low dword, short duration in high dword */
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#define MSR_PKG_POWER_LIMIT 0x610
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#define PKG_POWER_LIMIT_MASK 0x7fff
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#define PKG_POWER_LIMIT_EN (1 << 15)
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#define PKG_POWER_LIMIT_CLAMP (1 << 16)
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#define PKG_POWER_LIMIT_TIME_SHIFT 17
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#define PKG_POWER_LIMIT_TIME_MASK 0x7f
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#define MSR_VR_CURRENT_CONFIG 0x601
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#define MSR_VR_MISC_CONFIG 0x603
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#define MSR_PKG_POWER_SKU_UNIT 0x606
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#define MSR_PKG_POWER_SKU 0x614
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#define MSR_DDR_RAPL_LIMIT 0x618
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#define MSR_VR_MISC_CONFIG2 0x636
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#define MSR_PP0_POWER_LIMIT 0x638
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#define MSR_PP1_POWER_LIMIT 0x640
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#define MSR_CONFIG_TDP_NOMINAL 0x648
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#define MSR_CONFIG_TDP_LEVEL1 0x649
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#define MSR_CONFIG_TDP_LEVEL2 0x64a
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#define MSR_CONFIG_TDP_CONTROL 0x64b
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#define MSR_TURBO_ACTIVATION_RATIO 0x64c
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/* P-state configuration */
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#define PSS_MAX_ENTRIES 8
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#define PSS_RATIO_STEP 2
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#define PSS_LATENCY_TRANSITION 10
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#define PSS_LATENCY_BUSMASTER 10
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/* PCODE MMIO communications live in the MCHBAR. */
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#define BIOS_MAILBOX_INTERFACE 0x5da4
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109
src/soc/intel/broadwell/broadwell/msr.h
Normal file
109
src/soc/intel/broadwell/broadwell/msr.h
Normal file
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@ -0,0 +1,109 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef _BROADWELL_MSR_H_
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#define _BROADWELL_MSR_H_
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#define MSR_PIC_MSG_CONTROL 0x2e
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#define CORE_THREAD_COUNT_MSR 0x35
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#define IA32_FEATURE_CONTROL 0x3a
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#define CPUID_VMX (1 << 5)
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#define CPUID_SMX (1 << 6)
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#define MSR_PLATFORM_INFO 0xce
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#define PLATFORM_INFO_SET_TDP (1 << 29)
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#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
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#define MSR_PMG_IO_CAPTURE_BASE 0xe4
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#define MSR_FEATURE_CONFIG 0x13c
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#define SMM_MCA_CAP_MSR 0x17d
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#define SMM_CPU_SVRSTR_BIT 57
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#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32))
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#define MSR_FLEX_RATIO 0x194
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#define FLEX_RATIO_LOCK (1 << 20)
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#define FLEX_RATIO_EN (1 << 16)
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#define IA32_MISC_ENABLE 0x1a0
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#define MSR_MISC_PWR_MGMT 0x1aa
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#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
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#define MSR_TURBO_RATIO_LIMIT 0x1ad
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#define MSR_TEMPERATURE_TARGET 0x1a2
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#define IA32_PERF_CTL 0x199
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#define IA32_THERM_INTERRUPT 0x19b
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#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
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#define ENERGY_POLICY_PERFORMANCE 0
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#define ENERGY_POLICY_NORMAL 6
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#define ENERGY_POLICY_POWERSAVE 15
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#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
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#define EMRRphysBase_MSR 0x1f4
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#define EMRRphysMask_MSR 0x1f5
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#define IA32_PLATFORM_DCA_CAP 0x1f8
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#define MSR_POWER_CTL 0x1fc
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#define MSR_LT_LOCK_MEMORY 0x2e7
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#define UNCORE_EMRRphysBase_MSR 0x2f4
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#define UNCORE_EMRRphysMask_MSR 0x2f5
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#define IA32_MC0_STATUS 0x401
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#define SMM_FEATURE_CONTROL_MSR 0x4e0
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#define SMM_CPU_SAVE_EN (1 << 1)
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#define MSR_C_STATE_LATENCY_CONTROL_0 0x60a
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#define MSR_C_STATE_LATENCY_CONTROL_1 0x60b
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#define MSR_C_STATE_LATENCY_CONTROL_2 0x60c
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#define MSR_C_STATE_LATENCY_CONTROL_3 0x633
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#define MSR_C_STATE_LATENCY_CONTROL_4 0x634
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#define MSR_C_STATE_LATENCY_CONTROL_5 0x635
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#define IRTL_VALID (1 << 15)
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#define IRTL_1_NS (0 << 10)
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#define IRTL_32_NS (1 << 10)
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#define IRTL_1024_NS (2 << 10)
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#define IRTL_32768_NS (3 << 10)
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#define IRTL_1048576_NS (4 << 10)
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#define IRTL_33554432_NS (5 << 10)
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#define IRTL_RESPONSE_MASK (0x3ff)
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#define MSR_COUNTER_24_MHZ 0x637
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/* long duration in low dword, short duration in high dword */
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#define MSR_PKG_POWER_LIMIT 0x610
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#define PKG_POWER_LIMIT_MASK 0x7fff
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#define PKG_POWER_LIMIT_EN (1 << 15)
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#define PKG_POWER_LIMIT_CLAMP (1 << 16)
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#define PKG_POWER_LIMIT_TIME_SHIFT 17
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#define PKG_POWER_LIMIT_TIME_MASK 0x7f
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#define MSR_VR_CURRENT_CONFIG 0x601
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#define MSR_VR_MISC_CONFIG 0x603
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#define MSR_PKG_POWER_SKU_UNIT 0x606
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#define MSR_PKG_POWER_SKU 0x614
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#define MSR_DDR_RAPL_LIMIT 0x618
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#define MSR_VR_MISC_CONFIG2 0x636
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#define MSR_PP0_POWER_LIMIT 0x638
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#define MSR_PP1_POWER_LIMIT 0x640
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#define MSR_CONFIG_TDP_NOMINAL 0x648
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#define MSR_CONFIG_TDP_LEVEL1 0x649
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#define MSR_CONFIG_TDP_LEVEL2 0x64a
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#define MSR_CONFIG_TDP_CONTROL 0x64b
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#define MSR_TURBO_ACTIVATION_RATIO 0x64c
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/* SMM save state MSRs */
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#define SMBASE_MSR 0xc20
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#define IEDBASE_MSR 0xc22
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/* MTRRcap_MSR bits */
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#define SMRR_SUPPORTED (1<<11)
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#define EMRR_SUPPORTED (1<<12)
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#endif
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@ -20,8 +20,8 @@
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#include <stdint.h>
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#include <cpu/x86/msr.h>
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#include <timer.h>
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#include <broadwell/msr.h>
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#define MSR_COUNTER_24_MHz 0x637
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static struct monotonic_counter {
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int initialized;
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struct mono_time time;
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@ -34,7 +34,7 @@ static inline uint32_t read_counter_msr(void)
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* is polled frequently enough to only use the lower 32-bits. */
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msr_t counter_msr;
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counter_msr = rdmsr(MSR_COUNTER_24_MHz);
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counter_msr = rdmsr(MSR_COUNTER_24_MHZ);
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return counter_msr.lo;
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}
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@ -33,22 +33,8 @@
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#include <southbridge/intel/lynxpoint/pch.h>
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#include "haswell.h"
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#define EMRRphysBase_MSR 0x1f4
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#define EMRRphysMask_MSR 0x1f5
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#define UNCORE_EMRRphysBase_MSR 0x2f4
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#define UNCORE_EMRRphysMask_MSR 0x2f5
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#define SMM_MCA_CAP_MSR 0x17d
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#define SMM_CPU_SVRSTR_BIT 57
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#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32))
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#define SMM_FEATURE_CONTROL_MSR 0x4e0
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#define SMM_CPU_SAVE_EN (1 << 1)
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/* SMM save state MSRs */
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#define SMBASE_MSR 0xc20
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#define IEDBASE_MSR 0xc22
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#define SMRR_SUPPORTED (1<<11)
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#define EMRR_SUPPORTED (1<<12)
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#include <broadwell/cpu.h>
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#include <broadwell/msr.h>
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#include <broadwell/smm.h>
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#include <broadwell/systemagent.h>
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