tegra and tegra124: Bring up graphics
Changes to standard includes and files to define constants and prototypes. Code from nvidia that turns on the display, with lots of changes for coreboot. With this code, which is going to be cleaned up, we get a display in coreboot and depthcharge. BUG=None TEST=Builds, boots, and displays a color bar pattern from coreboot. Depthcharge starts up, and we see the dev mode scary screen, just in time for Halloween. BRANCH=None Change-Id: I0eada9a7386e6f623cf8708144b0f6e850e97d50 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/174613 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org>
This commit is contained in:
Ronald G. Minnich
chrome-internal-fetch
parent
74512b7ecf
commit
7e944208a1
9 changed files with 2593 additions and 45 deletions
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@ -27,6 +27,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select EC_GOOGLE_CHROMEEC_SPI
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select SOC_NVIDIA_TEGRA124
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select MAINBOARD_HAS_BOOTBLOCK_INIT
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select MAINBOARD_DO_NATIVE_VGA_INIT
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config MAINBOARD_DIR
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string
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@ -561,4 +561,5 @@ struct disp_ctl_win {
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};
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void display_startup(device_t dev);
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void dp_bringup(u32 winb_addr);
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#endif /* __SOC_NVIDIA_TEGRA_DC_H */
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316
src/soc/nvidia/tegra/displayport.h
Normal file
316
src/soc/nvidia/tegra/displayport.h
Normal file
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@ -0,0 +1,316 @@
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/*
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* drivers/video/tegra/dc/dpaux_regs.h
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*
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* Copyright (c) 2011, NVIDIA Corporation.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __SOC_NVIDIA_TEGRA_DISPLAYPORT_H__
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#define __SOC_NVIDIA_TEGRA_DISPLAYPORT_H__
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/* things we can't get rid of just yet. */
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#define DPAUX_INTR_EN_AUX (0x1)
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#define DPAUX_INTR_AUX (0x5)
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#define DPAUX_DP_AUXDATA_WRITE_W(i) (0x9 + 4*(i))
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#define DPAUX_DP_AUXDATA_READ_W(i) (0x19 + 4*(i))
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#define DPAUX_DP_AUXADDR (0x29)
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#define DPAUX_DP_AUXCTL (0x2d)
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#define DPAUX_DP_AUXCTL_CMDLEN_SHIFT (0)
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#define DPAUX_DP_AUXCTL_CMDLEN_FIELD (0xff)
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#define DPAUX_DP_AUXCTL_CMD_SHIFT (12)
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#define DPAUX_DP_AUXCTL_CMD_MASK (0xf << 12)
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#define DPAUX_DP_AUXCTL_CMD_I2CWR (0 << 12)
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#define DPAUX_DP_AUXCTL_CMD_I2CRD (1 << 12)
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#define DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT (2 << 12)
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#define DPAUX_DP_AUXCTL_CMD_MOTWR (4 << 12)
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#define DPAUX_DP_AUXCTL_CMD_MOTRD (5 << 12)
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#define DPAUX_DP_AUXCTL_CMD_MOTREQWSTAT (6 << 12)
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#define DPAUX_DP_AUXCTL_CMD_AUXWR (8 << 12)
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#define DPAUX_DP_AUXCTL_CMD_AUXRD (9 << 12)
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#define DPAUX_DP_AUXCTL_TRANSACTREQ_SHIFT (16)
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#define DPAUX_DP_AUXCTL_TRANSACTREQ_MASK (0x1 << 16)
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#define DPAUX_DP_AUXCTL_TRANSACTREQ_DONE (0 << 16)
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#define DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING (1 << 16)
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#define DPAUX_DP_AUXCTL_RST_SHIFT (31)
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#define DPAUX_DP_AUXCTL_RST_DEASSERT (0 << 31)
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#define DPAUX_DP_AUXCTL_RST_ASSERT (1 << 31)
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#define DPAUX_DP_AUXSTAT (0x31)
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#define DPAUX_DP_AUXSTAT_HPD_STATUS_SHIFT (28)
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#define DPAUX_DP_AUXSTAT_HPD_STATUS_UNPLUG (0 << 28)
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#define DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED (1 << 28)
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#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SHIFT (20)
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#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_MASK (0xf << 20)
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#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_IDLE (0 << 20)
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#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SYNC (1 << 20)
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#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_START1 (2 << 20)
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#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_COMMAND (3 << 20)
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#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_ADDRESS (4 << 20)
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#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_LENGTH (5 << 20)
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#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_WRITE1 (6 << 20)
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#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_READ1 (7 << 20)
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#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_GET_M (8 << 20)
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#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP1 (9 << 20)
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#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP2 (10 << 20)
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#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_REPLY (11 << 20)
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#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_CLEANUP (12 << 20)
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#define DPAUX_DP_AUXSTAT_REPLYTYPE_SHIFT (16)
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#define DPAUX_DP_AUXSTAT_REPLYTYPE_MASK (0xf << 16)
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#define DPAUX_DP_AUXSTAT_REPLYTYPE_ACK (0 << 16)
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#define DPAUX_DP_AUXSTAT_REPLYTYPE_NACK (1 << 16)
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#define DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER (2 << 16)
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#define DPAUX_DP_AUXSTAT_REPLYTYPE_I2CNACK (4 << 16)
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#define DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER (8 << 16)
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#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_SHIFT (11)
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#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_NOT_PENDING (0 << 11)
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#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING (1 << 11)
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#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_SHIFT (10)
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#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_NOT_PENDING (0 << 10)
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#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING (1 << 10)
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#define DPAUX_DP_AUXSTAT_RX_ERROR_SHIFT (9)
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#define DPAUX_DP_AUXSTAT_RX_ERROR_NOT_PENDING (0 << 9)
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#define DPAUX_DP_AUXSTAT_RX_ERROR_PENDING (1 << 9)
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#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_SHIFT (8)
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#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_NOT_PENDING (0 << 8)
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#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING (1 << 8)
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#define DPAUX_DP_AUXSTAT_REPLY_M_SHIFT (0)
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#define DPAUX_DP_AUXSTAT_REPLY_M_MASK (0xff << 0)
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#define DPAUX_HPD_CONFIG (0x3d)
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#define DPAUX_HPD_IRQ_CONFIG (0x41)
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#define DPAUX_DP_AUX_CONFIG (0x45)
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#define DPAUX_HYBRID_PADCTL (0x49)
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#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_SHIFT (15)
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#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_DISABLE (0 << 15)
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#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_ENABLE (1 << 15)
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#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_SHIFT (14)
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#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_DISABLE (0 << 14)
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#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_ENABLE (1 << 14)
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#define DPAUX_HYBRID_PADCTL_AUX_CMH_SHIFT (12)
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#define DPAUX_HYBRID_PADCTL_AUX_CMH_DEFAULT_MASK (0x3 << 12)
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#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_60 (0 << 12)
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#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_64 (1 << 12)
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#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_70 (2 << 12)
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#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_56 (3 << 12)
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#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_SHIFT (8)
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#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_DEFAULT_MASK (0x7 << 8)
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#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_78 (0 << 8)
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#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_60 (1 << 8)
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#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_54 (2 << 8)
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#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_45 (3 << 8)
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#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_50 (4 << 8)
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#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_42 (5 << 8)
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#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_39 (6 << 8)
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#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_34 (7 << 8)
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#define DPAUX_HYBRID_PADCTL_AUX_DRVI_SHIFT (2)
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#define DPAUX_HYBRID_PADCTL_AUX_DRVI_DEFAULT_MASK (0x3f << 2)
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#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_SHIFT (1)
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#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_DISABLE (0 << 1)
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#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE (1 << 1)
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#define DPAUX_HYBRID_PADCTL_MODE_SHIFT (0)
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#define DPAUX_HYBRID_PADCTL_MODE_AUX (0)
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#define DPAUX_HYBRID_PADCTL_MODE_I2C (1)
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#define DPAUX_HYBRID_SPARE (0x4d)
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#define DPAUX_HYBRID_SPARE_PAD_PWR_POWERUP (0)
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#define DPAUX_HYBRID_SPARE_PAD_PWR_POWERDOWN (1)
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/* TODO: figure out which of the NV_ constants are the same as all the other
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* display port standard constants.
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*/
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#define DP_AUX_DEFER_MAX_TRIES 7
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#define DP_AUX_TIMEOUT_MAX_TRIES 2
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#define DP_POWER_ON_MAX_TRIES 3
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#define DP_CLOCK_RECOVERY_MAX_TRIES 7
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#define DP_CLOCK_RECOVERY_TOT_TRIES 15
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#define DP_AUX_MAX_BYTES 16
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#define DP_LCDVCC_TO_HPD_DELAY_MS 200
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#define DP_AUX_TIMEOUT_MS 40
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#define DP_DPCP_RETRY_SLEEP_NS 400
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enum {
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driveCurrent_Level0 = 0,
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driveCurrent_Level1 = 1,
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driveCurrent_Level2 = 2,
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driveCurrent_Level3 = 3,
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};
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enum {
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preEmphasis_Disabled = 0,
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preEmphasis_Level1 = 1,
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preEmphasis_Level2 = 2,
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preEmphasis_Level3 = 3,
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};
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enum {
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postCursor2_Level0 = 0,
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postCursor2_Level1 = 1,
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postCursor2_Level2 = 2,
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postCursor2_Level3 = 3,
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postCursor2_Supported
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};
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/* the +10ms is the time for power rail going up from 10-90% or
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90%-10% on powerdown */
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/* Time from power-rail is turned on and aux/12c-over-aux is available */
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#define EDP_PWR_ON_TO_AUX_TIME_MS (200+10)
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/* Time from power-rail is turned on and MainLink is available for LT */
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#define EDP_PWR_ON_TO_ML_TIME_MS (200+10)
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/* Time from turning off power to turn-it on again (does not include post
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poweron time) */
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#define EDP_PWR_OFF_TO_ON_TIME_MS (500+10)
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struct tegra_dc_dp_data {
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struct tegra_dc *dc;
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struct tegra_dc_sor_data *sor;
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void *aux_base;
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struct tegra_dc_mode *mode;
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struct tegra_dc_dp_link_config link_cfg;
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};
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/* DPCD definitions */
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/* you know, all the vendors pick their own set of defines.
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* All of them.
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* FIXME so we can use the ones in include/device/drm_dp_helper.h
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*/
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#define NV_DPCD_REV (0x00000000)
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#define NV_DPCD_REV_MAJOR_SHIFT (4)
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#define NV_DPCD_REV_MAJOR_MASK (0xf << 4)
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#define NV_DPCD_REV_MINOR_SHIFT (0)
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#define NV_DPCD_REV_MINOR_MASK (0xf)
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#define NV_DPCD_MAX_LINK_BANDWIDTH (0x00000001)
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#define NV_DPCD_MAX_LINK_BANDWIDTH_VAL_1_62_GPBS (0x00000006)
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#define NV_DPCD_MAX_LINK_BANDWIDTH_VAL_2_70_GPBS (0x0000000a)
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#define NV_DPCD_MAX_LINK_BANDWIDTH_VAL_5_40_GPBS (0x00000014)
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#define NV_DPCD_MAX_LANE_COUNT (0x00000002)
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#define NV_DPCD_MAX_LANE_COUNT_MASK (0x1f)
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#define NV_DPCD_MAX_LANE_COUNT_LANE_1 (0x00000001)
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#define NV_DPCD_MAX_LANE_COUNT_LANE_2 (0x00000002)
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#define NV_DPCD_MAX_LANE_COUNT_LANE_4 (0x00000004)
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#define NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_NO (0x00000000 << 7)
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#define NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES (0x00000001 << 7)
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#define NV_DPCD_MAX_DOWNSPREAD (0x00000003)
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#define NV_DPCD_MAX_DOWNSPREAD_VAL_NONE (0x00000000)
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#define NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT (0x00000001)
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#define NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_F (0x00000000 << 6)
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#define NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_T (0x00000001 << 6)
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#define NV_DPCD_EDP_CONFIG_CAP (0x0000000D)
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#define NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_NO (0x00000000)
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#define NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES (0x00000001)
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#define NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_NO (0x00000000 << 1)
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#define NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES (0x00000001 << 1)
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#define NV_DPCD_LINK_BANDWIDTH_SET (0x00000100)
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#define NV_DPCD_LANE_COUNT_SET (0x00000101)
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#define NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_F (0x00000000 << 7)
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#define NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_T (0x00000001 << 7)
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#define NV_DPCD_TRAINING_PATTERN_SET (0x00000102)
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#define NV_DPCD_TRAINING_PATTERN_SET_TPS_MASK 0x3
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#define NV_DPCD_TRAINING_PATTERN_SET_TPS_NONE (0x00000000)
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#define NV_DPCD_TRAINING_PATTERN_SET_TPS_TP1 (0x00000001)
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#define NV_DPCD_TRAINING_PATTERN_SET_TPS_TP2 (0x00000002)
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#define NV_DPCD_TRAINING_PATTERN_SET_TPS_TP3 (0x00000003)
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#define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_F (0x00000000 << 5)
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#define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_T (0x00000001 << 5)
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#define NV_DPCD_TRAINING_LANE0_SET (0x00000103)
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#define NV_DPCD_TRAINING_LANE1_SET (0x00000104)
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#define NV_DPCD_TRAINING_LANE2_SET (0x00000105)
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#define NV_DPCD_TRAINING_LANE3_SET (0x00000106)
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#define NV_DPCD_TRAINING_LANEX_SET_DC_SHIFT 0
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#define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_T (0x00000001 << 2)
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#define NV_DPCD_TRAINING_LANEX_SET_PE_SHIFT 3
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#define NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_T (0x00000001 << 5)
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#define NV_DPCD_DOWNSPREAD_CTRL (0x00000107)
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#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_NONE (0x00000000 << 4)
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#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_LT_0_5 (0x00000001 << 4)
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#define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET (0x00000108)
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#define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_8B10B 1
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#define NV_DPCD_EDP_CONFIG_SET (0x0000010A)
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#define NV_DPCD_EDP_CONFIG_SET_ASC_RESET_DISABLE (0x00000000)
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#define NV_DPCD_EDP_CONFIG_SET_ASC_RESET_ENABLE (0x00000001)
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#define NV_DPCD_EDP_CONFIG_SET_FRAMING_CHANGE_DISABLE (0x00000000 << 1)
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#define NV_DPCD_EDP_CONFIG_SET_FRAMING_CHANGE_ENABLE (0x00000001 << 1)
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#define NV_DPCD_TRAINING_LANE0_1_SET2 (0x0000010F)
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#define NV_DPCD_TRAINING_LANE2_3_SET2 (0x00000110)
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#define NV_DPCD_LANEX_SET2_PC2_SHIFT 0
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#define NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_T (0x00000001 << 2)
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#define NV_DPCD_LANEXPLUS1_SET2_PC2_SHIFT 4
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#define NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_T (0x00000001 << 6)
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#define NV_DPCD_SINK_COUNT (0x00000200)
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#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR (0x00000201)
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#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTO_TEST_NO (0x00000000 << 1)
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#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTO_TEST_YES (0x00000001 << 1)
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#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_CP_NO (0x00000000 << 2)
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#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_CP_YES (0x00000001 << 2)
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#define NV_DPCD_LANE0_1_STATUS (0x00000202)
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#define NV_DPCD_LANE2_3_STATUS (0x00000203)
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#define NV_DPCD_STATUS_LANEX_CR_DONE_SHIFT 0
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#define NV_DPCD_STATUS_LANEX_CR_DONE_NO (0x00000000)
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#define NV_DPCD_STATUS_LANEX_CR_DONE_YES (0x00000001)
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#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT 1
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#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_NO (0x00000000 << 1)
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#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES (0x00000001 << 1)
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#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT 2
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#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_NO (0x00000000 << 2)
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#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES (0x00000001 << 2)
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#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_SHIFT 4
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#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_NO (0x00000000 << 4)
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#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES (0x00000001 << 4)
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#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT 5
|
||||
#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_NO (0x00000000 << 5)
|
||||
#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES (0x00000001 << 5)
|
||||
#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT 6
|
||||
#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_NO (0x00000000 << 6)
|
||||
#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES (0x00000001 << 6)
|
||||
#define NV_DPCD_LANE_ALIGN_STATUS_UPDATED (0x00000204)
|
||||
#define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_NO (0x00000000)
|
||||
#define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_YES (0x00000001)
|
||||
#define NV_DPCD_LANE0_1_ADJUST_REQ (0x00000206)
|
||||
#define NV_DPCD_LANE2_3_ADJUST_REQ (0x00000207)
|
||||
#define NV_DPCD_ADJUST_REQ_LANEX_DC_SHIFT 0
|
||||
#define NV_DPCD_ADJUST_REQ_LANEX_DC_MASK 0x3
|
||||
#define NV_DPCD_ADJUST_REQ_LANEX_PE_SHIFT 2
|
||||
#define NV_DPCD_ADJUST_REQ_LANEX_PE_MASK (0x3 << 2)
|
||||
#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_SHIFT 4
|
||||
#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_MASK (0x3 << 4)
|
||||
#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_SHIFT 6
|
||||
#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_MASK (0x3 << 6)
|
||||
#define NV_DPCD_ADJUST_REQ_POST_CURSOR2 (0x0000020C)
|
||||
#define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_MASK 0x3
|
||||
#define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_SHIFT(i) (i*2)
|
||||
#define NV_DPCD_TEST_REQUEST (0x00000218)
|
||||
#define NV_DPCD_SOURCE_IEEE_OUI (0x00000300)
|
||||
#define NV_DPCD_SINK_IEEE_OUI (0x00000400)
|
||||
#define NV_DPCD_BRANCH_IEEE_OUI (0x00000500)
|
||||
#define NV_DPCD_SET_POWER (0x00000600)
|
||||
#define NV_DPCD_SET_POWER_VAL_RESERVED (0x00000000)
|
||||
#define NV_DPCD_SET_POWER_VAL_D0_NORMAL (0x00000001)
|
||||
#define NV_DPCD_SET_POWER_VAL_D3_PWRDWN (0x00000002)
|
||||
#define NV_DPCD_HDCP_BKSV_OFFSET (0x00068000)
|
||||
#define NV_DPCD_HDCP_RPRIME_OFFSET (0x00068005)
|
||||
#define NV_DPCD_HDCP_AKSV_OFFSET (0x00068007)
|
||||
#define NV_DPCD_HDCP_AN_OFFSET (0x0006800C)
|
||||
#define NV_DPCD_HDCP_VPRIME_OFFSET (0x00068014)
|
||||
#define NV_DPCD_HDCP_BCAPS_OFFSET (0x00068028)
|
||||
#define NV_DPCD_HDCP_BSTATUS_OFFSET (0x00068029)
|
||||
#define NV_DPCD_HDCP_BINFO_OFFSET (0x0006802A)
|
||||
#define NV_DPCD_HDCP_KSV_FIFO_OFFSET (0x0006802C)
|
||||
#define NV_DPCD_HDCP_AINFO_OFFSET (0x0006803B)
|
||||
|
||||
int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
|
||||
u8 *data, u32 *size, u32 *aux_stat);
|
||||
int dpaux_write(u32 addr, u32 size, u32 data);
|
||||
int dpaux_read(u32 addr, u32 size, u8 *data);
|
||||
void debug_dpaux_print(u32 addr, u32 size);
|
||||
void dp_link_training(u32 lanes, u32 speed);
|
||||
#endif /* __SOC_NVIDIA_TEGRA_DISPLAYPORT_H__ */
|
||||
724
src/soc/nvidia/tegra/dp.c
Normal file
724
src/soc/nvidia/tegra/dp.c
Normal file
|
|
@ -0,0 +1,724 @@
|
|||
/*
|
||||
* drivers/video/tegra/dc/dp.c
|
||||
*
|
||||
* Copyright (c) 2011-2013, NVIDIA Corporation.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/i2c.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <delay.h>
|
||||
#include <soc/addressmap.h>
|
||||
#include "i2c.h"
|
||||
#include "dc.h"
|
||||
/* shit. This is broken. */
|
||||
#include <soc/nvidia/tegra124/sor.h>
|
||||
// this is really broken. #include <soc/ardpaux.h>
|
||||
#include <soc/nvidia/tegra/displayport.h>
|
||||
|
||||
#undef DEBUG
|
||||
extern int dump;
|
||||
unsigned long READL(void* p);
|
||||
void WRITEL(unsigned long value, void* p);
|
||||
|
||||
static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg)
|
||||
{
|
||||
void *addr = dp->aux_base + (u32)(reg <<2);
|
||||
u32 reg_val = READL(addr);
|
||||
#ifdef DEBUG
|
||||
|
||||
printk(BIOS_SPEW, "JZ: %s: reg: %p, val: %#x\n", __func__,
|
||||
addr, reg_val);
|
||||
#endif
|
||||
return reg_val;
|
||||
}
|
||||
|
||||
static inline void tegra_dpaux_writel(struct tegra_dc_dp_data *dp,
|
||||
u32 reg, u32 val)
|
||||
{
|
||||
void *addr = dp->aux_base + (u32)(reg <<2);
|
||||
#ifdef DEBUG
|
||||
printk(BIOS_SPEW, "JZ: %s: reg: %p, val: %#x\n", __func__,
|
||||
addr, val);
|
||||
#endif
|
||||
WRITEL(val, addr);
|
||||
}
|
||||
|
||||
|
||||
static inline u32 tegra_dc_dpaux_poll_register(struct tegra_dc_dp_data *dp,
|
||||
u32 reg, u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_ms)
|
||||
{
|
||||
// unsigned long timeout_jf = jiffies + msecs_to_jiffies(timeout_ms);
|
||||
u32 reg_val = 0;
|
||||
|
||||
printk(BIOS_SPEW, "JZ: %s: enter, poll_reg: %#x: timeout: 0x%x\n",
|
||||
__func__, reg*4, timeout_ms);
|
||||
do {
|
||||
// udelay(poll_interval_us);
|
||||
udelay(1);
|
||||
reg_val = tegra_dpaux_readl(dp, reg);
|
||||
} while (((reg_val & mask) != exp_val) && (--timeout_ms > 0));
|
||||
|
||||
if ((reg_val & mask) == exp_val)
|
||||
return 0; /* success */
|
||||
printk(BIOS_SPEW,"dpaux_poll_register 0x%x: timeout: (reg_val)0x%08x & (mask)0x%08x != (exp_val)0x%08x\n", reg, reg_val, mask, exp_val);
|
||||
return timeout_ms;
|
||||
}
|
||||
|
||||
|
||||
static inline int tegra_dpaux_wait_transaction(struct tegra_dc_dp_data *dp)
|
||||
{
|
||||
/* According to DP spec, each aux transaction needs to finish
|
||||
within 40ms. */
|
||||
if (tegra_dc_dpaux_poll_register(dp, DPAUX_DP_AUXCTL,
|
||||
DPAUX_DP_AUXCTL_TRANSACTREQ_MASK,
|
||||
DPAUX_DP_AUXCTL_TRANSACTREQ_DONE,
|
||||
100, DP_AUX_TIMEOUT_MS*1000) != 0) {
|
||||
printk(BIOS_SPEW,"dp: DPAUX transaction timeout\n");
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
|
||||
u32 addr, u8 *data, u32 *size, u32 *aux_stat)
|
||||
{
|
||||
int i;
|
||||
u32 reg_val;
|
||||
u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES;
|
||||
u32 defer_retries = DP_AUX_DEFER_MAX_TRIES;
|
||||
u32 temp_data;
|
||||
|
||||
if (*size > DP_AUX_MAX_BYTES)
|
||||
return -1; /* only write one chunk of data */
|
||||
|
||||
/* Make sure the command is write command */
|
||||
switch (cmd) {
|
||||
case DPAUX_DP_AUXCTL_CMD_I2CWR:
|
||||
case DPAUX_DP_AUXCTL_CMD_MOTWR:
|
||||
case DPAUX_DP_AUXCTL_CMD_AUXWR:
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_SPEW,"dp: aux write cmd 0x%x is invalid\n",
|
||||
cmd);
|
||||
return -1;
|
||||
}
|
||||
|
||||
#if 0
|
||||
/* interesting. */
|
||||
if (tegra_platform_is_silicon()) {
|
||||
*aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
|
||||
if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {
|
||||
printk(BIOS_SPEW,"dp: HPD is not detected\n");
|
||||
return -EFAULT;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr);
|
||||
for (i = 0; i < DP_AUX_MAX_BYTES/4; ++i) {
|
||||
memcpy(&temp_data, data, 4);
|
||||
tegra_dpaux_writel(dp, DPAUX_DP_AUXDATA_WRITE_W(i),
|
||||
temp_data);
|
||||
data += 4;
|
||||
}
|
||||
|
||||
reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL);
|
||||
reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK;
|
||||
reg_val |= cmd;
|
||||
reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD;
|
||||
reg_val |= ((*size-1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT);
|
||||
|
||||
while ((timeout_retries > 0) && (defer_retries > 0)) {
|
||||
if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) ||
|
||||
(defer_retries != DP_AUX_DEFER_MAX_TRIES))
|
||||
udelay(1);
|
||||
|
||||
reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING;
|
||||
tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val);
|
||||
|
||||
if (tegra_dpaux_wait_transaction(dp))
|
||||
printk(BIOS_SPEW,"dp: aux write transaction timeout\n");
|
||||
|
||||
*aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
|
||||
// printk(BIOS_SPEW, "dp: %s: aux stat: 0x%08x\n", __func__, *aux_stat);
|
||||
|
||||
/* Ignore I2C errors on fpga */
|
||||
if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) ||
|
||||
(*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) ||
|
||||
(*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) ||
|
||||
(*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) {
|
||||
if (timeout_retries-- > 0) {
|
||||
printk(BIOS_SPEW,"dp: aux write retry (0x%x) -- %d\n",
|
||||
*aux_stat, timeout_retries);
|
||||
/* clear the error bits */
|
||||
tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
|
||||
*aux_stat);
|
||||
continue;
|
||||
} else {
|
||||
printk(BIOS_SPEW,"dp: aux write got error (0x%x)\n",
|
||||
*aux_stat);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) ||
|
||||
(*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) {
|
||||
if (defer_retries-- > 0) {
|
||||
printk(BIOS_SPEW, "dp: aux write defer (0x%x) -- %d\n",
|
||||
*aux_stat, defer_retries);
|
||||
/* clear the error bits */
|
||||
tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
|
||||
*aux_stat);
|
||||
continue;
|
||||
} else {
|
||||
printk(BIOS_SPEW, "dp: aux write defer exceeds max retries "
|
||||
"(0x%x)\n",
|
||||
*aux_stat);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) ==
|
||||
DPAUX_DP_AUXSTAT_REPLYTYPE_ACK) {
|
||||
*size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK);
|
||||
return 0;
|
||||
} else {
|
||||
printk(BIOS_SPEW,"dp: aux write failed (0x%x)\n", *aux_stat);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
/* Should never come to here */
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int tegra_dc_dpaux_write(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
|
||||
u8 *data, u32 *size, u32 *aux_stat)
|
||||
{
|
||||
u32 cur_size = 0;
|
||||
u32 finished = 0;
|
||||
u32 cur_left;
|
||||
int ret = 0;
|
||||
|
||||
do {
|
||||
cur_size = *size - finished;
|
||||
if (cur_size > DP_AUX_MAX_BYTES)
|
||||
cur_size = DP_AUX_MAX_BYTES;
|
||||
cur_left = cur_size;
|
||||
ret = tegra_dc_dpaux_write_chunk(dp, cmd, addr,
|
||||
data, &cur_left, aux_stat);
|
||||
|
||||
cur_size -= cur_left;
|
||||
finished += cur_size;
|
||||
addr += cur_size;
|
||||
data += cur_size;
|
||||
|
||||
if (ret)
|
||||
break;
|
||||
} while (*size > finished);
|
||||
|
||||
*size = finished;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
|
||||
u32 addr, u8 *data, u32 *size, u32 *aux_stat)
|
||||
{
|
||||
u32 reg_val;
|
||||
u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES;
|
||||
u32 defer_retries = DP_AUX_DEFER_MAX_TRIES;
|
||||
|
||||
if (*size > DP_AUX_MAX_BYTES)
|
||||
return -1; /* only read one chunk */
|
||||
|
||||
/* Check to make sure the command is read command */
|
||||
switch (cmd) {
|
||||
case DPAUX_DP_AUXCTL_CMD_I2CRD:
|
||||
case DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT:
|
||||
case DPAUX_DP_AUXCTL_CMD_MOTRD:
|
||||
case DPAUX_DP_AUXCTL_CMD_AUXRD:
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_SPEW,"dp: aux read cmd 0x%x is invalid\n", cmd);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (0){
|
||||
*aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
|
||||
if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {
|
||||
printk(BIOS_SPEW,"dp: HPD is not detected\n");
|
||||
//return EFAULT;
|
||||
}
|
||||
}
|
||||
|
||||
tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr);
|
||||
|
||||
reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL);
|
||||
reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK;
|
||||
reg_val |= cmd;
|
||||
printk(BIOS_SPEW, "cmd = %08x\n", reg_val);
|
||||
reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD;
|
||||
reg_val |= ((*size-1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT);
|
||||
printk(BIOS_SPEW, "cmd = %08x\n", reg_val);
|
||||
while ((timeout_retries > 0) && (defer_retries > 0)) {
|
||||
if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) ||
|
||||
(defer_retries != DP_AUX_DEFER_MAX_TRIES))
|
||||
udelay(DP_DPCP_RETRY_SLEEP_NS * 2);
|
||||
|
||||
reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING;
|
||||
printk(BIOS_SPEW, "cmd = %08x\n", reg_val);
|
||||
tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val);
|
||||
|
||||
if (tegra_dpaux_wait_transaction(dp))
|
||||
printk(BIOS_SPEW,"dp: aux read transaction timeout\n");
|
||||
|
||||
*aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
|
||||
printk(BIOS_SPEW, "dp: %s: aux stat: 0x%08x\n", __func__, *aux_stat);
|
||||
|
||||
if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) ||
|
||||
(*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) ||
|
||||
(*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) ||
|
||||
(*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) {
|
||||
if (timeout_retries-- > 0) {
|
||||
printk(BIOS_SPEW, "dp: aux read retry (0x%x) -- %d\n",
|
||||
*aux_stat, timeout_retries);
|
||||
/* clear the error bits */
|
||||
tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
|
||||
*aux_stat);
|
||||
continue; /* retry */
|
||||
} else {
|
||||
printk(BIOS_SPEW,"dp: aux read got error (0x%x)\n",
|
||||
*aux_stat);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) ||
|
||||
(*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) {
|
||||
if (defer_retries-- > 0) {
|
||||
printk(BIOS_SPEW, "dp: aux read defer (0x%x) -- %d\n",
|
||||
*aux_stat, defer_retries);
|
||||
/* clear the error bits */
|
||||
tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
|
||||
*aux_stat);
|
||||
continue;
|
||||
} else {
|
||||
printk(BIOS_SPEW,"dp: aux read defer exceeds max retries "
|
||||
"(0x%x)\n", *aux_stat);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) ==
|
||||
DPAUX_DP_AUXSTAT_REPLYTYPE_ACK) {
|
||||
int i;
|
||||
u32 temp_data[4];
|
||||
|
||||
for (i = 0; i < DP_AUX_MAX_BYTES/4; ++i)
|
||||
temp_data[i] = tegra_dpaux_readl(dp,
|
||||
DPAUX_DP_AUXDATA_READ_W(i));
|
||||
|
||||
*size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK);
|
||||
printk(BIOS_SPEW, "dp: aux read data %d bytes\n", *size);
|
||||
memcpy(data, temp_data, *size);
|
||||
|
||||
return 0;
|
||||
} else {
|
||||
printk(BIOS_SPEW,"dp: aux read failed (0x%x\n", *aux_stat);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
/* Should never come to here */
|
||||
printk(BIOS_SPEW, "%s: can't\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
|
||||
u8 *data, u32 *size, u32 *aux_stat)
|
||||
{
|
||||
u32 finished = 0;
|
||||
u32 cur_size;
|
||||
int ret = 0;
|
||||
|
||||
do {
|
||||
cur_size = *size - finished;
|
||||
if (cur_size > DP_AUX_MAX_BYTES)
|
||||
cur_size = DP_AUX_MAX_BYTES;
|
||||
|
||||
ret = tegra_dc_dpaux_read_chunk(dp, cmd, addr,
|
||||
data, &cur_size, aux_stat);
|
||||
|
||||
/* cur_size should be the real size returned */
|
||||
addr += cur_size;
|
||||
data += cur_size;
|
||||
finished += cur_size;
|
||||
|
||||
if (ret)
|
||||
break;
|
||||
|
||||
#if 0
|
||||
if (cur_size == 0) {
|
||||
printk(BIOS_SPEW,"JZ: no data found, ret\n");
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
} while (*size > finished);
|
||||
|
||||
*size = finished;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data *dp, u32 cmd,
|
||||
u8 *data_ptr)
|
||||
{
|
||||
u32 size = 1;
|
||||
u32 status = 0;
|
||||
int ret;
|
||||
|
||||
ret = tegra_dc_dpaux_read_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
|
||||
cmd, data_ptr, &size, &status);
|
||||
if (ret)
|
||||
printk(BIOS_SPEW,"dp: Failed to read DPCD data. CMD 0x%x, Status 0x%x\n",
|
||||
cmd, status);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#if 0
|
||||
static void tegra_dc_dpaux_enable(struct tegra_dc_dp_data *dp)
|
||||
{
|
||||
/* clear interrupt */
|
||||
tegra_dpaux_writel(dp, DPAUX_INTR_AUX, 0xffffffff);
|
||||
/* do not enable interrupt for now. Enable them when Isr in place */
|
||||
tegra_dpaux_writel(dp, DPAUX_INTR_EN_AUX, 0x0);
|
||||
|
||||
tegra_dpaux_writel(dp, DPAUX_HYBRID_PADCTL,
|
||||
DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_50 |
|
||||
DPAUX_HYBRID_PADCTL_AUX_CMH_V0_70 |
|
||||
0x18 << DPAUX_HYBRID_PADCTL_AUX_DRVI_SHIFT |
|
||||
DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE);
|
||||
}
|
||||
|
||||
static int tegra_dc_dp_lower_config(struct tegra_dc_dp_data *dp,
|
||||
struct tegra_dc_dp_link_config *cfg)
|
||||
{
|
||||
if (cfg->link_bw == SOR_LINK_SPEED_G1_62) {
|
||||
if (cfg->max_link_bw > SOR_LINK_SPEED_G1_62)
|
||||
cfg->link_bw = SOR_LINK_SPEED_G2_7;
|
||||
cfg->lane_count /= 2;
|
||||
} else if (cfg->link_bw == SOR_LINK_SPEED_G2_7)
|
||||
cfg->link_bw = SOR_LINK_SPEED_G1_62;
|
||||
else if (cfg->link_bw == SOR_LINK_SPEED_G5_4) {
|
||||
if (cfg->lane_count == 1) {
|
||||
cfg->link_bw = SOR_LINK_SPEED_G2_7;
|
||||
cfg->lane_count = cfg->max_lane_count;
|
||||
} else
|
||||
cfg->lane_count /= 2;
|
||||
} else {
|
||||
printk(BIOS_ERR,
|
||||
"dp: Error link rate %d\n", cfg->link_bw);
|
||||
return 0;
|
||||
}
|
||||
return (cfg->lane_count > 0);
|
||||
}
|
||||
|
||||
#endif
|
||||
static int tegra_dc_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp,
|
||||
struct tegra_dc_dp_link_config *cfg)
|
||||
{
|
||||
u8 dpcd_data;
|
||||
int ret;
|
||||
|
||||
ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LANE_COUNT,
|
||||
&dpcd_data);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
cfg->max_lane_count = dpcd_data & NV_DPCD_MAX_LANE_COUNT_MASK;
|
||||
printk(BIOS_SPEW, "JZ: %s: max_lane_count: %d\n", __func__, cfg->max_lane_count);
|
||||
|
||||
cfg->support_enhanced_framing =
|
||||
(dpcd_data & NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES) ?
|
||||
1 : 0;
|
||||
printk(BIOS_SPEW, "JZ: %s: enh-framing: %d\n", __func__, cfg->support_enhanced_framing);
|
||||
|
||||
ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_DOWNSPREAD,
|
||||
&dpcd_data);
|
||||
if (ret)
|
||||
return ret;
|
||||
cfg->downspread = (dpcd_data & NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT) ?
|
||||
1 : 0;
|
||||
printk(BIOS_SPEW, "JZ: %s: downspread: %d\n", __func__, cfg->downspread);
|
||||
|
||||
ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LINK_BANDWIDTH,
|
||||
&cfg->max_link_bw);
|
||||
if (ret)
|
||||
return ret;
|
||||
printk(BIOS_SPEW, "JZ: %s: max_link_bw: %d\n", __func__, cfg->max_link_bw);
|
||||
|
||||
// jz, changed
|
||||
// cfg->bits_per_pixel = dp->dc->pdata->default_out->depth;
|
||||
cfg->bits_per_pixel = 24;
|
||||
|
||||
/* TODO: need to come from the board file */
|
||||
/* Venice2 settings */
|
||||
cfg->drive_current = 0x20202020;
|
||||
cfg->preemphasis = 0;
|
||||
cfg->postcursor = 0;
|
||||
|
||||
ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_EDP_CONFIG_CAP,
|
||||
&dpcd_data);
|
||||
if (ret)
|
||||
return ret;
|
||||
cfg->alt_scramber_reset_cap =
|
||||
(dpcd_data & NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES) ?
|
||||
1 : 0;
|
||||
cfg->only_enhanced_framing =
|
||||
(dpcd_data & NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES) ?
|
||||
1 : 0;
|
||||
printk(BIOS_SPEW, "JZ: %s: alt_reset_cap: %d, only_enh_framing: %d\n", __func__,
|
||||
cfg->alt_scramber_reset_cap, cfg->only_enhanced_framing);
|
||||
|
||||
cfg->lane_count = cfg->max_lane_count;
|
||||
cfg->link_bw = cfg->max_link_bw;
|
||||
cfg->enhanced_framing = cfg->support_enhanced_framing;
|
||||
|
||||
#if 0 // jz
|
||||
tegra_dc_dp_calc_config(dp, dp->mode, cfg);
|
||||
return 0;
|
||||
#else
|
||||
// return -1; // do link_training
|
||||
return 0; // do link_training
|
||||
#endif // jz
|
||||
}
|
||||
|
||||
|
||||
#if 0
|
||||
static int tegra_dc_dp_explore_link_cfg(struct tegra_dc_dp_data *dp,
|
||||
struct tegra_dc_dp_link_config *cfg, struct tegra_dc_mode *mode)
|
||||
{
|
||||
struct tegra_dc_dp_link_config temp_cfg;
|
||||
#if 0
|
||||
/* kernel thing. */
|
||||
if (!mode->pclk || !mode->h_active || !mode->v_active) {
|
||||
dev_err(&dp->dc->ndev->dev,
|
||||
"dp: error mode configuration");
|
||||
return -EINVAL;
|
||||
}
|
||||
#endif
|
||||
if (!cfg->max_link_bw || !cfg->max_lane_count) {
|
||||
printk(BIOS_SPEW,
|
||||
"dp: error link configuration");
|
||||
return -1;
|
||||
}
|
||||
|
||||
cfg->is_valid = 0;
|
||||
memcpy(&temp_cfg, cfg, sizeof(temp_cfg));
|
||||
|
||||
temp_cfg.link_bw = temp_cfg.max_link_bw;
|
||||
temp_cfg.lane_count = temp_cfg.max_lane_count;
|
||||
|
||||
while (tegra_dc_dp_calc_config(dp, mode, &temp_cfg) &&
|
||||
tegra_dp_link_config(dp, &temp_cfg)) {
|
||||
/* current link cfg is doable */
|
||||
memcpy(cfg, &temp_cfg, sizeof(temp_cfg));
|
||||
|
||||
/* try to lower the config */
|
||||
if (!tegra_dc_dp_lower_config(dp, &temp_cfg))
|
||||
break;
|
||||
}
|
||||
|
||||
return cfg->is_valid ? 0 : -1;
|
||||
}
|
||||
#endif
|
||||
#if 0
|
||||
static long tegra_dc_dp_setup_clk(struct tegra_dc *dc, struct clk *clk)
|
||||
{
|
||||
struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
|
||||
struct clk *sor_clk = dp->sor->sor_clk;
|
||||
struct clk *parent_clk;
|
||||
|
||||
if (clk == dc->clk) {
|
||||
parent_clk = clk_get_sys(NULL,
|
||||
dc->out->parent_clk ? : "pll_d_out0");
|
||||
if (clk_get_parent(clk) != parent_clk)
|
||||
clk_set_parent(clk, parent_clk);
|
||||
}
|
||||
|
||||
tegra_dc_sor_setup_clk(dp->sor, clk, false);
|
||||
|
||||
parent_clk = clk_get(NULL, "pll_dp");
|
||||
|
||||
if (clk_get_parent(sor_clk) != parent_clk)
|
||||
clk_set_parent(sor_clk, parent_clk);
|
||||
clk_set_rate(parent_clk, 270000000);
|
||||
|
||||
if (!tegra_is_clk_enabled(parent_clk))
|
||||
clk_prepare_enable(parent_clk);
|
||||
|
||||
return tegra_dc_pclk_round_rate(dc, dp->sor->dc->mode.pclk);
|
||||
}
|
||||
|
||||
#endif
|
||||
//struct tegra_dc dc_data = {0};
|
||||
struct tegra_dc_sor_data sor_data = {0};
|
||||
struct tegra_dc_dp_data dp_data = {0};
|
||||
|
||||
static int tegra_dc_dpcd_read_rev(struct tegra_dc_dp_data *dp,
|
||||
u8 *rev)
|
||||
{
|
||||
u32 size;
|
||||
int ret;
|
||||
u32 status = 0;
|
||||
|
||||
size = 3;
|
||||
ret = tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
|
||||
NV_DPCD_REV, rev, &size, &status);
|
||||
if (ret) {
|
||||
printk(BIOS_SPEW,"dp: Failed to read NV_DPCD_REV\n");
|
||||
return ret;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
u32 dp_setup_timing(u32 panel_id, u32 width, u32 height);
|
||||
void dp_bringup(u32 winb_addr)
|
||||
{
|
||||
struct tegra_dc_dp_data *dp = &dp_data;
|
||||
|
||||
u32 dpcd_rev;
|
||||
u32 pclk_freq;
|
||||
// int ret;
|
||||
|
||||
printk(BIOS_SPEW, "JZ: %s: entry\n",__func__);
|
||||
|
||||
dp->sor = &sor_data;
|
||||
// dp->sor->dc = dc;
|
||||
dp->sor->base = (void *)TEGRA_ARM_SOR;
|
||||
// dp->sor->base_res = base_res;
|
||||
// dp->sor->sor_clk = clk;
|
||||
dp->sor->link_cfg = &dp->link_cfg;
|
||||
dp->sor->portnum = 0;
|
||||
|
||||
dp->aux_base = (void *)TEGRA_ARM_DPAUX;
|
||||
/* dp->mode = 0; */ /* ???? */
|
||||
|
||||
/* read panel info */
|
||||
if (!tegra_dc_dpcd_read_rev(dp, (u8 *)&dpcd_rev)) {
|
||||
printk(BIOS_SPEW,"PANEL info: \n");
|
||||
printk(BIOS_SPEW,"--DPCP version(%#x): %d.%d\n",
|
||||
dpcd_rev, (dpcd_rev >> 4)&0x0f, (dpcd_rev & 0x0f));
|
||||
}
|
||||
|
||||
if (tegra_dc_dp_init_max_link_cfg(dp, &dp->link_cfg))
|
||||
printk(BIOS_SPEW,"dp: failed to init link configuration\n");
|
||||
#if 0
|
||||
if (tegra_dc_dp_link_training(dp, &dp->link_cfg))
|
||||
printk(BIOS_SPEW,"dp: failed to do lt\n");
|
||||
#endif
|
||||
|
||||
dp_link_training((u32)(dp->link_cfg.lane_count),
|
||||
(u32)(dp->link_cfg.link_bw));
|
||||
|
||||
pclk_freq = dp_setup_timing(5, 2560, 1700); // W: 2560, H: 1700, use_plld2: 1
|
||||
printk(BIOS_SPEW, "JZ: %s: pclk_freq: %d\n",__func__, pclk_freq);
|
||||
|
||||
// void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr)
|
||||
void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr,
|
||||
u32 lane_count, u32 enhanced_framing, u32 panel_edp,
|
||||
u32 pclkfreq, u32 linkfreq);
|
||||
|
||||
dp_misc_setting(dp->link_cfg.bits_per_pixel,
|
||||
2560, 1700, winb_addr,
|
||||
(u32)dp->link_cfg.lane_count,
|
||||
(u32)dp->link_cfg.enhanced_framing,
|
||||
(u32)dp->link_cfg.alt_scramber_reset_cap,
|
||||
pclk_freq,
|
||||
dp->link_cfg.link_bw * 27);
|
||||
void dp_test(void);
|
||||
//dp_test();
|
||||
|
||||
|
||||
#if 0 // jz, next
|
||||
else if (tegra_dc_dp_explore_link_cfg(dp, &dp->link_cfg,
|
||||
dp->mode))
|
||||
printk(BIOS_SPEW,"dp irq: cannot get working config\n");
|
||||
|
||||
// if (tegra_dp_link_config(dp, &dp->link_cfg))
|
||||
// printk(BIOS_SPEW,"dp: failed to set link configuration\n");
|
||||
#endif // rgm
|
||||
}
|
||||
|
||||
void debug_dpaux_print(u32 addr, u32 size)
|
||||
{
|
||||
struct tegra_dc_dp_data *dp = &dp_data;
|
||||
u32 status = 0;
|
||||
u8 buf[16];
|
||||
int i;
|
||||
|
||||
if ((size == 0) || (size > 16)) {
|
||||
printk(BIOS_SPEW,"dp: %s: invalid size %d\n", __func__, size);
|
||||
return;
|
||||
}
|
||||
|
||||
if (tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
|
||||
addr, buf, &size, &status)) {
|
||||
printk(BIOS_SPEW,"******AuxRead Error: 0x%04x: status 0x%08x\n", addr, status);
|
||||
return;
|
||||
}
|
||||
printk(BIOS_SPEW, "%s: addr: 0x%04x, size: %d\n", __func__, addr, size);
|
||||
for (i=0; i < size; ++i)
|
||||
printk(BIOS_SPEW," %02x", buf[i]);
|
||||
|
||||
printk(BIOS_SPEW,"\n");
|
||||
}
|
||||
|
||||
int dpaux_read(u32 addr, u32 size, u8 *data)
|
||||
{
|
||||
|
||||
struct tegra_dc_dp_data *dp = &dp_data;
|
||||
u32 status = 0;
|
||||
|
||||
if ((size == 0) || (size > 16)) {
|
||||
printk(BIOS_SPEW,"dp: %s: invalid size %d\n", __func__, size);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
|
||||
addr, data, &size, &status)) {
|
||||
printk(BIOS_SPEW,"dp: Failed to read reg %#x, status: %#x\n", addr, status);
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dpaux_write(u32 addr, u32 size, u32 data)
|
||||
{
|
||||
struct tegra_dc_dp_data *dp = &dp_data;
|
||||
u32 status = 0;
|
||||
int ret;
|
||||
|
||||
printk(BIOS_SPEW, "JZ: %s: entry, addr: 0x%08x, size: 0x%08x, data: %#x\n",
|
||||
__func__, addr, size, data);
|
||||
|
||||
ret = tegra_dc_dpaux_write(dp, DPAUX_DP_AUXCTL_CMD_AUXWR,
|
||||
addr, (u8 *)&data, &size, &status);
|
||||
if (ret)
|
||||
printk(BIOS_SPEW,"dp: Failed to write to reg %#x, status: 0x%x\n",
|
||||
addr, status);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -39,12 +39,14 @@ ramstage-y += cbfs.c
|
|||
ramstage-y += cbmem.c
|
||||
ramstage-y += cpug.S
|
||||
ramstage-y += clock.c
|
||||
ramstage-y += display.c
|
||||
ramstage-y += display.c displayhack.c
|
||||
ramstage-y += dma.c
|
||||
ramstage-y += i2c.c
|
||||
ramstage-y += monotonic_timer.c
|
||||
ramstage-y += soc.c
|
||||
ramstage-y += sor.c
|
||||
ramstage-y += spi.c
|
||||
ramstage-y += ../tegra/dp.c
|
||||
ramstage-y += ../tegra/gpio.c
|
||||
ramstage-y += ../tegra/i2c.c
|
||||
ramstage-y += ../tegra/pinmux.c
|
||||
|
|
|
|||
|
|
@ -30,11 +30,31 @@
|
|||
#include <cpu/cpu.h>
|
||||
#include <boot/tables.h>
|
||||
#include <cbmem.h>
|
||||
#include <edid.h>
|
||||
#include <soc/clock.h>
|
||||
#include <soc/nvidia/tegra/dc.h>
|
||||
#include "chip.h"
|
||||
#include <soc/display.h>
|
||||
|
||||
int dump = 0;
|
||||
unsigned long READL(void * p);
|
||||
void WRITEL(unsigned long value, void * p);
|
||||
unsigned long READL(void * p)
|
||||
{
|
||||
unsigned long value = readl(p);
|
||||
if (dump)
|
||||
printk(BIOS_SPEW, "readl %p %08lx\n", p, value);
|
||||
return value;
|
||||
}
|
||||
|
||||
|
||||
void WRITEL(unsigned long value, void * p)
|
||||
{
|
||||
if (dump)
|
||||
printk(BIOS_SPEW, "writel %p %08lx\n", p, value);
|
||||
writel(value, p);
|
||||
}
|
||||
|
||||
static const u32 rgb_enb_tab[PIN_REG_COUNT] = {
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
|
|
@ -73,25 +93,25 @@ static int update_display_mode(struct dc_disp_reg *disp,
|
|||
u32 rate;
|
||||
u32 div;
|
||||
|
||||
writel(0x0, &disp->disp_timing_opt);
|
||||
WRITEL(0x0, &disp->disp_timing_opt);
|
||||
|
||||
writel(config->vref_to_sync << 16 | config->href_to_sync,
|
||||
WRITEL(config->vref_to_sync << 16 | config->href_to_sync,
|
||||
&disp->ref_to_sync);
|
||||
writel(config->vsync_width << 16 | config->hsync_width, &disp->sync_width);
|
||||
writel(config->vback_porch << 16 | config->hback_porch, &disp->back_porch);
|
||||
writel(config->vfront_porch << 16 | config->hfront_porch,
|
||||
WRITEL(config->vsync_width << 16 | config->hsync_width, &disp->sync_width);
|
||||
WRITEL(config->vback_porch << 16 | config->hback_porch, &disp->back_porch);
|
||||
WRITEL(config->vfront_porch << 16 | config->hfront_porch,
|
||||
&disp->front_porch);
|
||||
|
||||
writel(config->xres | (config->yres << 16), &disp->disp_active);
|
||||
WRITEL(config->xres | (config->yres << 16), &disp->disp_active);
|
||||
|
||||
val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
|
||||
val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
|
||||
writel(val, &disp->data_enable_opt);
|
||||
WRITEL(val, &disp->data_enable_opt);
|
||||
|
||||
val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
|
||||
val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
|
||||
val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
|
||||
writel(val, &disp->disp_interface_ctrl);
|
||||
WRITEL(val, &disp->disp_interface_ctrl);
|
||||
|
||||
/*
|
||||
* The pixel clock divider is in 7.1 format (where the bottom bit
|
||||
|
|
@ -104,11 +124,11 @@ static int update_display_mode(struct dc_disp_reg *disp,
|
|||
div = ((rate * 2 + config->pixel_clock / 2) / config->pixel_clock) - 2;
|
||||
printk(BIOS_SPEW, "Display clock %d, divider %d\n", rate, div);
|
||||
|
||||
writel(0x00010001, &disp->shift_clk_opt);
|
||||
WRITEL(0x00010001, &disp->shift_clk_opt);
|
||||
|
||||
val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT;
|
||||
val |= div << SHIFT_CLK_DIVIDER_SHIFT;
|
||||
writel(val, &disp->disp_clk_ctrl);
|
||||
WRITEL(val, &disp->disp_clk_ctrl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -154,55 +174,55 @@ static void update_window(struct display_controller *dc,
|
|||
u32 h_dda, v_dda;
|
||||
u32 val;
|
||||
|
||||
val = readl(&dc->cmd.disp_win_header);
|
||||
val = READL(&dc->cmd.disp_win_header);
|
||||
val |= WINDOW_A_SELECT;
|
||||
writel(val, &dc->cmd.disp_win_header);
|
||||
WRITEL(val, &dc->cmd.disp_win_header);
|
||||
|
||||
writel(win->fmt, &dc->win.color_depth);
|
||||
WRITEL(win->fmt, &dc->win.color_depth);
|
||||
|
||||
clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK,
|
||||
BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT);
|
||||
|
||||
val = win->out_x << H_POSITION_SHIFT;
|
||||
val |= win->out_y << V_POSITION_SHIFT;
|
||||
writel(val, &dc->win.pos);
|
||||
WRITEL(val, &dc->win.pos);
|
||||
|
||||
val = win->out_w << H_SIZE_SHIFT;
|
||||
val |= win->out_h << V_SIZE_SHIFT;
|
||||
writel(val, &dc->win.size);
|
||||
WRITEL(val, &dc->win.size);
|
||||
|
||||
val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT;
|
||||
val |= win->h << V_PRESCALED_SIZE_SHIFT;
|
||||
writel(val, &dc->win.prescaled_size);
|
||||
WRITEL(val, &dc->win.prescaled_size);
|
||||
|
||||
writel(0, &dc->win.h_initial_dda);
|
||||
writel(0, &dc->win.v_initial_dda);
|
||||
WRITEL(0, &dc->win.h_initial_dda);
|
||||
WRITEL(0, &dc->win.v_initial_dda);
|
||||
|
||||
h_dda = (win->w * 0x1000) / MAX(win->out_w - 1, 1);
|
||||
v_dda = (win->h * 0x1000) / MAX(win->out_h - 1, 1);
|
||||
|
||||
val = h_dda << H_DDA_INC_SHIFT;
|
||||
val |= v_dda << V_DDA_INC_SHIFT;
|
||||
writel(val, &dc->win.dda_increment);
|
||||
WRITEL(val, &dc->win.dda_increment);
|
||||
|
||||
writel(win->stride, &dc->win.line_stride);
|
||||
writel(0, &dc->win.buf_stride);
|
||||
WRITEL(win->stride, &dc->win.line_stride);
|
||||
WRITEL(0, &dc->win.buf_stride);
|
||||
|
||||
val = WIN_ENABLE;
|
||||
if (win->bpp < 24)
|
||||
val |= COLOR_EXPAND;
|
||||
writel(val, &dc->win.win_opt);
|
||||
WRITEL(val, &dc->win.win_opt);
|
||||
|
||||
writel((u32) win->phys_addr, &dc->winbuf.start_addr);
|
||||
writel(win->x, &dc->winbuf.addr_h_offset);
|
||||
writel(win->y, &dc->winbuf.addr_v_offset);
|
||||
WRITEL((u32) win->phys_addr, &dc->winbuf.start_addr);
|
||||
WRITEL(win->x, &dc->winbuf.addr_h_offset);
|
||||
WRITEL(win->y, &dc->winbuf.addr_v_offset);
|
||||
|
||||
writel(0xff00, &dc->win.blend_nokey);
|
||||
writel(0xff00, &dc->win.blend_1win);
|
||||
WRITEL(0xff00, &dc->win.blend_nokey);
|
||||
WRITEL(0xff00, &dc->win.blend_1win);
|
||||
|
||||
val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
|
||||
val |= GENERAL_UPDATE | WIN_A_UPDATE;
|
||||
writel(val, &dc->cmd.state_ctrl);
|
||||
WRITEL(val, &dc->cmd.state_ctrl);
|
||||
}
|
||||
|
||||
/* this is really aimed at the lcd panel. That said, there are two display
|
||||
|
|
@ -279,38 +299,72 @@ void display_startup(device_t dev)
|
|||
* light things up here once we're sure it's all working.
|
||||
*/
|
||||
|
||||
writel(0x00000100, &dc->cmd.gen_incr_syncpt_ctrl);
|
||||
writel(0x0000011a, &dc->cmd.cont_syncpt_vsync);
|
||||
writel(0x00000000, &dc->cmd.int_type);
|
||||
writel(0x00000000, &dc->cmd.int_polarity);
|
||||
writel(0x00000000, &dc->cmd.int_mask);
|
||||
writel(0x00000000, &dc->cmd.int_enb);
|
||||
/* init dc_a */
|
||||
init_dca_regs();
|
||||
/* init sor */
|
||||
init_sor_regs();
|
||||
|
||||
/* init dpaux */
|
||||
init_dpaux_regs();
|
||||
|
||||
/* power up perip */
|
||||
dp_io_powerup();
|
||||
|
||||
/* bringup dp */
|
||||
dp_bringup(framebuffer_base_mb*MiB);
|
||||
|
||||
{ u16 *cp = (void *)(framebuffer_base_mb*MiB);
|
||||
for(i = 0; i < 1048576*8; i++)
|
||||
if (i %(2560/2) < 1280/2)
|
||||
cp[i] = 0x222;
|
||||
else
|
||||
cp[i] = 0x888;
|
||||
}
|
||||
|
||||
/* tell depthcharge ...
|
||||
*/
|
||||
struct edid edid;
|
||||
edid.x_resolution = 2560;
|
||||
edid.y_resolution = 1700;
|
||||
edid.bytes_per_line = 2560 * 2;
|
||||
edid.framebuffer_bits_per_pixel = 16;
|
||||
set_vbe_mode_info_valid(&edid, (uintptr_t)(framebuffer_base_mb*MiB));
|
||||
|
||||
if (0){
|
||||
/* do we still need these? */
|
||||
WRITEL(0x00000100, &dc->cmd.gen_incr_syncpt_ctrl);
|
||||
WRITEL(0x0000011a, &dc->cmd.cont_syncpt_vsync);
|
||||
WRITEL(0x00000000, &dc->cmd.int_type);
|
||||
WRITEL(0x00000000, &dc->cmd.int_polarity);
|
||||
WRITEL(0x00000000, &dc->cmd.int_mask);
|
||||
WRITEL(0x00000000, &dc->cmd.int_enb);
|
||||
|
||||
val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE;
|
||||
val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE;
|
||||
val |= PM1_ENABLE;
|
||||
writel(val, &dc->cmd.disp_pow_ctrl);
|
||||
WRITEL(val, &dc->cmd.disp_pow_ctrl);
|
||||
|
||||
val = readl(&dc->cmd.disp_cmd);
|
||||
val = READL(&dc->cmd.disp_cmd);
|
||||
val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT;
|
||||
writel(val, &dc->cmd.disp_cmd);
|
||||
WRITEL(val, &dc->cmd.disp_cmd);
|
||||
|
||||
writel(0x00000020, &dc->disp.mem_high_pri);
|
||||
writel(0x00000001, &dc->disp.mem_high_pri_timer);
|
||||
WRITEL(0x00000020, &dc->disp.mem_high_pri);
|
||||
WRITEL(0x00000001, &dc->disp.mem_high_pri_timer);
|
||||
|
||||
for (i = 0; i < PIN_REG_COUNT; i++) {
|
||||
writel(rgb_enb_tab[i], &dc->com.pin_output_enb[i]);
|
||||
writel(rgb_polarity_tab[i], &dc->com.pin_output_polarity[i]);
|
||||
writel(rgb_data_tab[i], &dc->com.pin_output_data[i]);
|
||||
WRITEL(rgb_enb_tab[i], &dc->com.pin_output_enb[i]);
|
||||
WRITEL(rgb_polarity_tab[i], &dc->com.pin_output_polarity[i]);
|
||||
WRITEL(rgb_data_tab[i], &dc->com.pin_output_data[i]);
|
||||
}
|
||||
|
||||
for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++)
|
||||
writel(rgb_sel_tab[i], &dc->com.pin_output_sel[i]);
|
||||
WRITEL(rgb_sel_tab[i], &dc->com.pin_output_sel[i]);
|
||||
|
||||
if (config->pixel_clock)
|
||||
update_display_mode(&dc->disp, config);
|
||||
|
||||
if (!setup_window(&window, config))
|
||||
update_window(dc, &window, config);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
1444
src/soc/nvidia/tegra124/displayhack.c
Normal file
1444
src/soc/nvidia/tegra124/displayhack.c
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -32,6 +32,8 @@ enum {
|
|||
TEGRA_ARM_PERIPHBASE = 0x50040000,
|
||||
TEGRA_ARM_DISPLAYA = 0x54200000,
|
||||
TEGRA_ARM_DISPLAYB = 0x54240000,
|
||||
TEGRA_ARM_SOR = 0x54540000,
|
||||
TEGRA_ARM_DPAUX = 0x545c0000,
|
||||
TEGRA_PG_UP_BASE = 0x60000000,
|
||||
TEGRA_TMRUS_BASE = 0x60005010,
|
||||
TEGRA_CLK_RST_BASE = 0x60006000,
|
||||
|
|
|
|||
|
|
@ -18,5 +18,8 @@
|
|||
#define __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_DISPLAY_H__
|
||||
|
||||
void setup_display(struct soc_nvidia_tegra124_config *config);
|
||||
|
||||
void init_dca_regs(void);
|
||||
void init_dpaux_regs(void);
|
||||
void init_sor_regs(void);
|
||||
void dp_io_powerup(void);
|
||||
#endif /* __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_DISPLAY_H__ */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue