erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

tegra124: Run bootblock and ROM stage out of DRAM.

Browse source 
To allow doing DRAM initialization in ROM stage instead of BootROM, we need to
move bootblock and ROM stage base address into iRAM, also the stack and CBFS
cache area just like TTB.

BUG=none
TEST=Boots on Nyan without problem.

Change-Id: I459faef5eb0f75561089dafbb111ae83729c3a29
Reviewed-on: https://chromium-review.googlesource.com/179822
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
This commit is contained in:
Hung-Te Lin 2013-12-12 19:45:52 +08:00 • committed by chrome-internal-fetch
commit 2d3ec06ec3
1 changed files with 11 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

16
src/soc/nvidia/tegra124/Kconfig
View file

@ -32,8 +32,14 @@ config BOOTBLOCK_CPU_INIT
# 0x4000_0000 BootROM runtime data/stack area, can be reclaimed after BootROM.
# +0000 (BootROM) Boot Information Table.
# +0100 (BootROM) BCT.
# ---------------------------------------------------------------------
# +0000 (Coreboot) TTB 16KB.
# +4000 (Coreboot) Stack.
# 0x4000_E000 Valid for anything to be executed after BootROM (effective entry
# point address specified in BCT).
# +0000 (Coreboot) Bootblock (max 36k).
# +9000 (Coreboot) ROM stage (max 36k).
# 0x4002_0000 (Coreboot) Cache of CBFS.
# 0x4003_FFFF End of iRAM.
config BOOTBLOCK_ROM_OFFSET
@ -54,11 +60,11 @@ config SYS_SDRAM_BASE
config BOOTBLOCK_BASE
hex
default 0x80000000
default 0x4000e000
config ROMSTAGE_BASE
hex
default 0x80100000
default 0x40017000
config RAMSTAGE_BASE
hex
@ -66,11 +72,11 @@ config RAMSTAGE_BASE
config STACK_TOP
hex
default 0x80400000
default 0x4000c000
config STACK_BOTTOM
hex
default 0x803f8000
default 0x40004000
config STACK_SIZE
hex
@ -83,7 +89,7 @@ config TTB_BUFFER
config CBFS_CACHE_ADDRESS
hex "memory address to put CBFS cache data"
default 0x803c0000
default 0x40020000
config CBFS_CACHE_SIZE
hex "size of CBFS cache data"