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baytrail: make caching MRC data more robust

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The NVM routines weren't propagaing the error codes up
the stack properly. Additionally, padding at the end
wasn't being zero'd correctly as the size of the cache
metadata wasn't being taken into account. The mrc_slot_valid()
wasn't failing as one would expect because of a fence post
issue. These changes should make debugging in this area a lot
easier in the future.

BUG=chrome-os-partner:25577
BRANCH=baytrail
TEST=Was able to identify errors when erasing failed.

Change-Id: I6a93586237763facb0a672d579b9b97ec6968440
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/185875
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Aaron Durbin 2014-02-11 15:05:08 -06:00 • committed by chrome-internal-fetch
commit b5e10ad47b
2 changed files with 10 additions and 13 deletions
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17
src/soc/intel/baytrail/mrc_cache.c
View file

@ -117,10 +117,6 @@ static int __mrc_cache_get_current(const struct mrc_data_region *region,
{
const struct mrc_saved_data *msd;
const struct mrc_saved_data *verified_cache;
uintptr_t region_end;
region_end = (uintptr_t)region->base;
region_end += region->size;
msd = region->base;
@ -178,8 +174,8 @@ int mrc_cache_stash_data(void *data, size_t size)
return -1;
}
/* Clear alignment padding bytes. */
memset(&cache->data[size], 0, cbmem_size - size);
/* Clear alignment padding bytes at end of data. */
memset(&cache->data[size], 0, cbmem_size - size - sizeof(*cache));
printk(BIOS_DEBUG, "Relocate MRC DATA from %p to %p (%u bytes)\n",
data, cache, size);
@ -210,7 +206,7 @@ static int mrc_slot_valid(const struct mrc_data_region *region,
size = to_save->size + sizeof(*to_save);
slot_end = slot_begin + size;
if (slot_begin < region_begin || slot_begin > region_end)
if (slot_begin < region_begin || slot_begin >= region_end)
return 0;
if (size > region->size)
@ -289,8 +285,11 @@ static void update_mrc_cache(void *unused)
next_slot = region.base;
}
nvm_write((void *)next_slot, current_boot,
current_boot->size + sizeof(*current_boot));
if (nvm_write((void *)next_slot, current_boot,
current_boot->size + sizeof(*current_boot))) {
printk(BIOS_DEBUG, "Failure writing MRC cache to %p.\n",
next_slot);
}
}
BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = {

6
src/soc/intel/baytrail/nvm.c
View file

@ -70,8 +70,7 @@ int nvm_erase(void *start, size_t size)
{
if (nvm_init() < 0)
return -1;
flash->erase(flash, to_flash_offset(start), size);
return 0;
return flash->erase(flash, to_flash_offset(start), size);
}
/* Write data to NVM. Returns 0 on success < 0 on error. */
@ -79,6 +78,5 @@ int nvm_write(void *start, const void *data, size_t size)
{
if (nvm_init() < 0)
return -1;
flash->write(flash, to_flash_offset(start), size, data);
return 0;
return flash->write(flash, to_flash_offset(start), size, data);
}