tegra124: Add an soc.c which sets up the chip operations and memory resource.

With this memory resource, the payload loading code can allocate a bounce
buffer and load the payload successfully. Depthcharge still doesn't start, but
that's probably because it's not finding the coreboot tables for some reason.

BUG=None
TEST=Built and booted to the payload on nyan.
BRANCH=None

Change-Id: I12f1d3d14c40776698077aab383dfd4b22054441
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/173543
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>

src/soc/nvidia/tegra124/Makefile.inc

@@ -34,6 +34,7 @@ ramstage-y += cbfs.c
 ramstage-y += cbmem.c
 ramstage-y += dma.c
 ramstage-y += monotonic_timer.c
+ramstage-y += soc.c
 ramstage-y += spi.c
 ramstage-y += timer.c
 ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c

src/soc/nvidia/tegra124/soc.c

@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+
+static void soc_enable(device_t dev)
+{
+	ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE >> 10UL,
+			     CONFIG_DRAM_SIZE_MB << 10UL);
+}
+
+static void soc_init(device_t dev)
+{
+	printk(BIOS_INFO, "CPU: Tegra124\n");
+}
+
+static void soc_noop(device_t dev)
+{
+}
+
+static struct device_operations soc_ops = {
+	.read_resources   = soc_noop,
+	.set_resources    = soc_noop,
+	.enable_resources = soc_enable,
+	.init             = soc_init,
+	.scan_bus         = 0,
+};
+
+static void enable_tegra124_dev(device_t dev)
+{
+	dev->ops = &soc_ops;
+}
+
+struct chip_operations soc_nvidia_tegra124_ops = {
+	CHIP_NAME("SOC Nvidia Tegra124")
+	.enable_dev = enable_tegra124_dev,
+};