broadwell: Clean up ACPI NVS region
Removed unused variables from the ACPI NVS region and separate out the variables used to communicate SerialIO base address and enable status. Some now unused ACPI methods in globalnvs.asl have been removed. BUG=chrome-os-partner:28234 TEST=None Change-Id: I20e26c7ebfb25975f315c3e41e67fee3f50df539 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198897 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
chrome-internal-fetch
parent
63ec6438b5
commit
d83cc82c36
4 changed files with 155 additions and 302 deletions
51
src/soc/intel/broadwell/acpi/device_nvs.asl
Normal file
51
src/soc/intel/broadwell/acpi/device_nvs.asl
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@ -0,0 +1,51 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* Device Enabled in ACPI Mode */
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S0EN, 8, // DMA Enable
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S1EN, 8, // I2C0 Enable
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S2EN, 8, // I2C1 Enable
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S3EN, 8, // SPI0 Enable
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S4EN, 8, // SPI1 Enable
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S5EN, 8, // UART0 Enable
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S6EN, 8, // UART1 Enable
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S7EN, 8, // SDIO Enable
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/* BAR 0 */
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S0B0, 32, // DMA BAR0
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S1B0, 32, // I2C0 BAR0
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S2B0, 32, // I2C1 BAR0
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S3B0, 32, // SPI0 BAR0
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S4B0, 32, // SPI1 BAR0
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S5B0, 32, // UART0 BAR0
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S6B0, 32, // UART1 BAR0
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S7B0, 32, // SDIO BAR0
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/* BAR 1 */
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S0B1, 32, // DMA BAR1
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S1B1, 32, // I2C0 BAR1
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S2B1, 32, // I2C1 BAR1
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S3B1, 32, // SPI0 BAR1
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S4B1, 32, // SPI1 BAR1
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S5B1, 32, // UART0 BAR1
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S6B1, 32, // UART1 BAR1
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S7B1, 32, // SDIO BAR1
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@ -29,182 +29,70 @@ Name(\DSEN, 1) // Display Output Switching Enable
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* we have to fix it up in coreboot's ACPI creation phase.
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*/
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OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0xf00)
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OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0x2000)
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Field (GNVS, ByteAcc, NoLock, Preserve)
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{
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/* Miscellaneous */
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Offset (0x00),
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OSYS, 16, // 0x00 - Operating System
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SMIF, 8, // 0x02 - SMI function
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PRM0, 8, // 0x03 - SMI function parameter
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PRM1, 8, // 0x04 - SMI function parameter
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SCIF, 8, // 0x05 - SCI function
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PRM2, 8, // 0x06 - SCI function parameter
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PRM3, 8, // 0x07 - SCI function parameter
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LCKF, 8, // 0x08 - Global Lock function for EC
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PRM4, 8, // 0x09 - Lock function parameter
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PRM5, 8, // 0x0a - Lock function parameter
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P80D, 32, // 0x0b - Debug port (IO 0x80) value
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LIDS, 8, // 0x0f - LID state (open = 1)
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PWRS, 8, // 0x10 - Power State (AC = 1)
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/* Thermal policy */
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Offset (0x11),
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TLVL, 8, // 0x11 - Throttle Level Limit
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FLVL, 8, // 0x12 - Current FAN Level
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TCRT, 8, // 0x13 - Critical Threshold
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TPSV, 8, // 0x14 - Passive Threshold
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TMAX, 8, // 0x15 - CPU Tj_max
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F0OF, 8, // 0x16 - FAN 0 OFF Threshold
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F0ON, 8, // 0x17 - FAN 0 ON Threshold
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F0PW, 8, // 0x18 - FAN 0 PWM value
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F1OF, 8, // 0x19 - FAN 1 OFF Threshold
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F1ON, 8, // 0x1a - FAN 1 ON Threshold
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F1PW, 8, // 0x1b - FAN 1 PWM value
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F2OF, 8, // 0x1c - FAN 2 OFF Threshold
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F2ON, 8, // 0x1d - FAN 2 ON Threshold
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F2PW, 8, // 0x1e - FAN 2 PWM value
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F3OF, 8, // 0x1f - FAN 3 OFF Threshold
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F3ON, 8, // 0x20 - FAN 3 ON Threshold
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F3PW, 8, // 0x21 - FAN 3 PWM value
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F4OF, 8, // 0x22 - FAN 4 OFF Threshold
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F4ON, 8, // 0x23 - FAN 4 ON Threshold
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F4PW, 8, // 0x24 - FAN 4 PWM value
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TMPS, 8, // 0x25 - Temperature Sensor ID
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/* Processor Identification */
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Offset (0x28),
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APIC, 8, // 0x28 - APIC Enabled by coreboot
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MPEN, 8, // 0x29 - Multi Processor Enable
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PCP0, 8, // 0x2a - PDC CPU/CORE 0
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PCP1, 8, // 0x2b - PDC CPU/CORE 1
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PPCM, 8, // 0x2c - Max. PPC state
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PCNT, 8, // 0x2d - Processor count
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/* Super I/O & CMOS config */
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Offset (0x32),
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NATP, 8, // 0x32 -
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S5U0, 8, // 0x33 - Enable USB0 in S5
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S5U1, 8, // 0x34 - Enable USB1 in S5
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S3U0, 8, // 0x35 - Enable USB0 in S3
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S3U1, 8, // 0x36 - Enable USB1 in S3
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S33G, 8, // 0x37 - Enable 3G in S3
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CMEM, 32, // 0x38 - CBMEM TOC
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/* Integrated Graphics Device */
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Offset (0x3c),
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IGDS, 8, // 0x3c - IGD state (primary = 1)
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TLST, 8, // 0x3d - Display Toggle List pointer
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CADL, 8, // 0x3e - Currently Attached Devices List
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PADL, 8, // 0x3f - Previously Attached Devices List
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CSTE, 16, // 0x40 - Current display state
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NSTE, 16, // 0x42 - Next display state
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SSTE, 16, // 0x44 - Set display state
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Offset (0x46),
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NDID, 8, // 0x46 - Number of Device IDs
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DID1, 32, // 0x47 - Device ID 1
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DID2, 32, // 0x4b - Device ID 2
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DID3, 32, // 0x4f - Device ID 3
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DID4, 32, // 0x53 - Device ID 4
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DID5, 32, // 0x57 - Device ID 5
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/* TPM support */
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Offset (0x5b),
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TPMP, 8, // 0x5b - TPM Present
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TPME, 8, // 0x5c - TPM Enable
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/* LynxPoint Serial IO device BARs */
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Offset (0x60),
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S0B0, 32, // 0x60 - D21:F0 Serial IO SDMA BAR0
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S1B0, 32, // 0x64 - D21:F1 Serial IO I2C0 BAR0
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S2B0, 32, // 0x68 - D21:F2 Serial IO I2C1 BAR0
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S3B0, 32, // 0x6c - D21:F3 Serial IO SPI0 BAR0
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S4B0, 32, // 0x70 - D21:F4 Serial IO SPI1 BAR0
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S5B0, 32, // 0x74 - D21:F5 Serial IO UAR0 BAR0
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S6B0, 32, // 0x78 - D21:F6 Serial IO UAR1 BAR0
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S7B0, 32, // 0x7c - D23:F0 Serial IO SDIO BAR0
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S0B1, 32, // 0x80 - D21:F0 Serial IO SDMA BAR1
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S1B1, 32, // 0x84 - D21:F1 Serial IO I2C0 BAR1
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S2B1, 32, // 0x88 - D21:F2 Serial IO I2C1 BAR1
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S3B1, 32, // 0x8c - D21:F3 Serial IO SPI0 BAR1
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S4B1, 32, // 0x90 - D21:F4 Serial IO SPI1 BAR1
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S5B1, 32, // 0x94 - D21:F5 Serial IO UAR0 BAR1
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S6B1, 32, // 0x98 - D21:F6 Serial IO UAR1 BAR1
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S7B1, 32, // 0x9c - D23:F0 Serial IO SDIO BAR1
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Offset (0xa0),
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CBMC, 32, // 0xa0 - coreboot mem console pointer
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/* IGD OpRegion */
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Offset (0xb4),
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ASLB, 32, // 0xb4 - IGD OpRegion Base Address
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IBTT, 8, // 0xb8 - IGD boot panel device
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IPAT, 8, // 0xb9 - IGD panel type cmos option
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ITVF, 8, // 0xba - IGD TV format cmos option
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ITVM, 8, // 0xbb - IGD TV minor format option
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IPSC, 8, // 0xbc - IGD panel scaling
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IBLC, 8, // 0xbd - IGD BLC config
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IBIA, 8, // 0xbe - IGD BIA config
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ISSC, 8, // 0xbf - IGD SSC config
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I409, 8, // 0xc0 - IGD 0409 modified settings
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I509, 8, // 0xc1 - IGD 0509 modified settings
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I609, 8, // 0xc2 - IGD 0609 modified settings
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I709, 8, // 0xc3 - IGD 0709 modified settings
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IDMM, 8, // 0xc4 - IGD Power conservation feature
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IDMS, 8, // 0xc5 - IGD DVMT memory size
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IF1E, 8, // 0xc6 - IGD function 1 enable
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HVCO, 8, // 0xc7 - IGD HPLL VCO
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NXD1, 32, // 0xc8 - IGD _DGS next DID1
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NXD2, 32, // 0xcc - IGD _DGS next DID2
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NXD3, 32, // 0xd0 - IGD _DGS next DID3
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NXD4, 32, // 0xd4 - IGD _DGS next DID4
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NXD5, 32, // 0xd8 - IGD _DGS next DID5
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NXD6, 32, // 0xdc - IGD _DGS next DID6
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NXD7, 32, // 0xe0 - IGD _DGS next DID7
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NXD8, 32, // 0xe4 - IGD _DGS next DID8
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ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI)
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PAVP, 8, // 0xe9 - IGD PAVP data
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Offset (0xeb),
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OSCC, 8, // 0xeb - PCIe OSC control
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NPCE, 8, // 0xec - native pcie support
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PLFL, 8, // 0xed - platform flavor
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BREV, 8, // 0xee - board revision
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DPBM, 8, // 0xef - digital port b mode
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DPCM, 8, // 0xf0 - digital port c mode
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DPDM, 8, // 0xf1 - digital port d mode
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ALFP, 8, // 0xf2 - active lfp
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IMON, 8, // 0xf3 - current graphics turbo imon value
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MMIO, 8, // 0xf4 - 64bit mmio support
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SMIF, 8, // 0x02 - SMI function
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PRM0, 8, // 0x03 - SMI function parameter
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PRM1, 8, // 0x04 - SMI function parameter
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SCIF, 8, // 0x05 - SCI function
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PRM2, 8, // 0x06 - SCI function parameter
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PRM3, 8, // 0x07 - SCI function parameter
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LCKF, 8, // 0x08 - Global Lock function for EC
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PRM4, 8, // 0x09 - Lock function parameter
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PRM5, 8, // 0x0a - Lock function parameter
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PCNT, 8, // 0x0b - Processor Count
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PPCM, 8, // 0x0c - Max PPC State
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TMPS, 8, // 0x0d - Temperature Sensor ID
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TLVL, 8, // 0x0e - Throttle Level Limit
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FLVL, 8, // 0x0f - Current FAN Level
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TCRT, 8, // 0x10 - Critical Threshold
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TPSV, 8, // 0x11 - Passive Threshold
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TMAX, 8, // 0x12 - CPU Tj_max
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TPMP, 8, // 0x13 - TPM Present
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S5U0, 8, // 0x14 - Enable USB in S5
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S3U0, 8, // 0x15 - Enable USB in S3
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S33G, 8, // 0x16 - Enable 3G in S3
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LIDS, 8, // 0x17 - LID State
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PWRS, 8, // 0x18 - AC Power State
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CMEM, 32, // 0x19 - 0x1c - CBMEM TOC
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CBMC, 32, // 0x1d - 0x20 - Coreboot Memory Console
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PM1I, 32, // 0x21 - 0x24 - PM1 wake status bit
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/* ChromeOS specific */
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Offset (0x100),
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#include <vendorcode/google/chromeos/acpi/gnvs.asl>
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/* Device specific */
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Offset (0x1000),
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#include "device_nvs.asl"
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}
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/* Set flag to enable USB charging in S3 */
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Method (S3UE)
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{
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Store (One, \S3U0)
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Store (One, \S3U1)
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}
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/* Set flag to disable USB charging in S3 */
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Method (S3UD)
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{
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Store (Zero, \S3U0)
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Store (Zero, \S3U1)
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}
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/* Set flag to enable USB charging in S5 */
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Method (S5UE)
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{
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Store (One, \S5U0)
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Store (One, \S5U1)
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}
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/* Set flag to disable USB charging in S5 */
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Method (S5UD)
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{
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Store (Zero, \S5U0)
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Store (Zero, \S5U1)
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}
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/* Set flag to enable 3G module in S3 */
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@ -218,66 +106,3 @@ Method (S3GD)
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{
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Store (Zero, \S33G)
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}
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External (\_TZ.THRM)
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External (\_TZ.SKIN)
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Method (TZUP)
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{
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/* Update Primary Thermal Zone */
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If (CondRefOf (\_TZ.THRM, Local0)) {
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Notify (\_TZ.THRM, 0x81)
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}
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/* Update Secondary Thermal Zone */
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If (CondRefOf (\_TZ.SKIN, Local0)) {
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Notify (\_TZ.SKIN, 0x81)
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}
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}
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/* Update Fan 0 thresholds */
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Method (F0UT, 2)
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{
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Store (Arg0, \F0OF)
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Store (Arg1, \F0ON)
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TZUP ()
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}
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/* Update Fan 1 thresholds */
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Method (F1UT, 2)
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{
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Store (Arg0, \F1OF)
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Store (Arg1, \F1ON)
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TZUP ()
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}
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/* Update Fan 2 thresholds */
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Method (F2UT, 2)
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{
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Store (Arg0, \F2OF)
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Store (Arg1, \F2ON)
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TZUP ()
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}
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/* Update Fan 3 thresholds */
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Method (F3UT, 2)
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{
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Store (Arg0, \F3OF)
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Store (Arg1, \F3ON)
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TZUP ()
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}
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/* Update Fan 4 thresholds */
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Method (F4UT, 2)
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{
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Store (Arg0, \F4OF)
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Store (Arg1, \F4ON)
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TZUP ()
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}
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/* Update Temperature Sensor ID */
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Method (TMPU, 1)
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{
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Store (Arg0, \TMPS)
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TZUP ()
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}
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43
src/soc/intel/broadwell/broadwell/device_nvs.h
Normal file
43
src/soc/intel/broadwell/broadwell/device_nvs.h
Normal file
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@ -0,0 +1,43 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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||||
* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; version 2 of the License.
|
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*
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef _BROADWELL_DEVICE_NVS_H_
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#define _BROADWELL_DEVICE_NVS_H_
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#include <stdint.h>
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/* Offset in Global NVS where this structure lives */
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#define DEVICE_NVS_OFFSET 0x1000
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#define SIO_NVS_DMA 0
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#define SIO_NVS_I2C0 1
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#define SIO_NVS_I2C1 2
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#define SIO_NVS_SPI0 3
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#define SIO_NVS_SPI1 4
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#define SIO_NVS_UART0 5
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#define SIO_NVS_UART1 6
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#define SIO_NVS_SDIO 7
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typedef struct {
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u8 enable[8];
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u32 bar0[8];
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u32 bar1[8];
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} __attribute__((packed)) device_nvs_t;
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#endif
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@ -18,7 +18,12 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "vendorcode/google/chromeos/gnvs.h"
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#ifndef _BROADWELL_NVS_H_
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#define _BROADWELL_NVS_H_
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#include <vendorcode/google/chromeos/gnvs.h>
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#include <broadwell/device_nvs.h>
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typedef struct {
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/* Miscellaneous */
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u16 osys; /* 0x00 - Operating System */
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@ -31,106 +36,35 @@ typedef struct {
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u8 lckf; /* 0x08 - Global Lock function for EC */
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u8 prm4; /* 0x09 - Lock function parameter */
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u8 prm5; /* 0x0a - Lock function parameter */
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u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
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u8 lids; /* 0x0f - LID state (open = 1) */
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u8 pwrs; /* 0x10 - Power state (AC = 1) */
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/* Thermal policy */
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u8 tlvl; /* 0x11 - Throttle Level Limit */
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u8 flvl; /* 0x12 - Current FAN Level */
|
||||
u8 tcrt; /* 0x13 - Critical Threshold */
|
||||
u8 tpsv; /* 0x14 - Passive Threshold */
|
||||
u8 tmax; /* 0x15 - CPU Tj_max */
|
||||
u8 f0of; /* 0x16 - FAN 0 OFF Threshold */
|
||||
u8 f0on; /* 0x17 - FAN 0 ON Threshold */
|
||||
u8 f0pw; /* 0x18 - FAN 0 PWM value */
|
||||
u8 f1of; /* 0x19 - FAN 1 OFF Threshold */
|
||||
u8 f1on; /* 0x1a - FAN 1 ON Threshold */
|
||||
u8 f1pw; /* 0x1b - FAN 1 PWM value */
|
||||
u8 f2of; /* 0x1c - FAN 2 OFF Threshold */
|
||||
u8 f2on; /* 0x1d - FAN 2 ON Threshold */
|
||||
u8 f2pw; /* 0x1e - FAN 2 PWM value */
|
||||
u8 f3of; /* 0x1f - FAN 3 OFF Threshold */
|
||||
u8 f3on; /* 0x20 - FAN 3 ON Threshold */
|
||||
u8 f3pw; /* 0x21 - FAN 3 PWM value */
|
||||
u8 f4of; /* 0x22 - FAN 4 OFF Threshold */
|
||||
u8 f4on; /* 0x23 - FAN 4 ON Threshold */
|
||||
u8 f4pw; /* 0x24 - FAN 4 PWM value */
|
||||
u8 tmps; /* 0x25 - Temperature Sensor ID */
|
||||
u8 rsvd3[2];
|
||||
/* Processor Identification */
|
||||
u8 apic; /* 0x28 - APIC enabled */
|
||||
u8 mpen; /* 0x29 - MP capable/enabled */
|
||||
u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
|
||||
u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */
|
||||
u8 ppcm; /* 0x2c - Max. PPC state */
|
||||
u8 pcnt; /* 0x2d - Processor Count */
|
||||
u8 rsvd4[4];
|
||||
/* Super I/O & CMOS config */
|
||||
u8 natp; /* 0x32 - SIO type */
|
||||
u8 s5u0; /* 0x33 - Enable USB0 in S5 */
|
||||
u8 s5u1; /* 0x34 - Enable USB1 in S5 */
|
||||
u8 s3u0; /* 0x35 - Enable USB0 in S3 */
|
||||
u8 s3u1; /* 0x36 - Enable USB1 in S3 */
|
||||
u8 s33g; /* 0x37 - Enable S3 in 3G */
|
||||
u32 cmem; /* 0x38 - CBMEM TOC */
|
||||
/* Integrated Graphics Device */
|
||||
u8 igds; /* 0x3c - IGD state */
|
||||
u8 tlst; /* 0x3d - Display Toggle List Pointer */
|
||||
u8 cadl; /* 0x3e - currently attached devices */
|
||||
u8 padl; /* 0x3f - previously attached devices */
|
||||
u16 cste; /* 0x40 - current display state */
|
||||
u16 nste; /* 0x42 - next display state */
|
||||
u16 sste; /* 0x44 - set display state */
|
||||
u8 ndid; /* 0x46 - number of device ids */
|
||||
u32 did[5]; /* 0x47 - 5b device id 1..5 */
|
||||
/* TPM support */
|
||||
u8 tpmp; /* 0x5b - TPM Present */
|
||||
u8 tpme; /* 0x5c - TPM Enable */
|
||||
u8 rsvd5[3];
|
||||
/* LynxPoint Serial IO device BARs */
|
||||
u32 s0b[8]; /* 0x60 - 0x7f - BAR0 */
|
||||
u32 s1b[8]; /* 0x80 - 0x9f - BAR1 */
|
||||
u32 cbmc; /* 0xa0 - 0xa3 - coreboot memconsole */
|
||||
u8 rsvd6[16];
|
||||
/* IGD OpRegion (not implemented yet) */
|
||||
u32 aslb; /* 0xb4 - IGD OpRegion Base Address */
|
||||
u8 ibtt; /* 0xb8 - IGD boot type */
|
||||
u8 ipat; /* 0xb9 - IGD panel type */
|
||||
u8 itvf; /* 0xba - IGD TV format */
|
||||
u8 itvm; /* 0xbb - IGD TV minor format */
|
||||
u8 ipsc; /* 0xbc - IGD Panel Scaling */
|
||||
u8 iblc; /* 0xbd - IGD BLC configuration */
|
||||
u8 ibia; /* 0xbe - IGD BIA configuration */
|
||||
u8 issc; /* 0xbf - IGD SSC configuration */
|
||||
u8 i409; /* 0xc0 - IGD 0409 modified settings */
|
||||
u8 i509; /* 0xc1 - IGD 0509 modified settings */
|
||||
u8 i609; /* 0xc2 - IGD 0609 modified settings */
|
||||
u8 i709; /* 0xc3 - IGD 0709 modified settings */
|
||||
u8 idmm; /* 0xc4 - IGD Power Conservation */
|
||||
u8 idms; /* 0xc5 - IGD DVMT memory size */
|
||||
u8 if1e; /* 0xc6 - IGD Function 1 Enable */
|
||||
u8 hvco; /* 0xc7 - IGD HPLL VCO */
|
||||
u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */
|
||||
u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */
|
||||
u8 pavp; /* 0xe9 - IGD PAVP data */
|
||||
u8 rsvd12; /* 0xea - rsvd */
|
||||
u8 oscc; /* 0xeb - PCIe OSC control */
|
||||
u8 npce; /* 0xec - native pcie support */
|
||||
u8 plfl; /* 0xed - platform flavor */
|
||||
u8 brev; /* 0xee - board revision */
|
||||
u8 dpbm; /* 0xef - digital port b mode */
|
||||
u8 dpcm; /* 0xf0 - digital port c mode */
|
||||
u8 dpdm; /* 0xf1 - digital port c mode */
|
||||
u8 alfp; /* 0xf2 - active lfp */
|
||||
u8 imon; /* 0xf3 - current graphics turbo imon value */
|
||||
u8 mmio; /* 0xf4 - 64bit mmio support */
|
||||
u8 rsvd13[11]; /* 0xf5 - rsvd */
|
||||
u8 pcnt; /* 0x0b - Processor Count */
|
||||
u8 ppcm; /* 0x0c - Max PPC State */
|
||||
u8 tmps; /* 0x0d - Temperature Sensor ID */
|
||||
u8 tlvl; /* 0x0e - Throttle Level Limit */
|
||||
u8 flvl; /* 0x0f - Current FAN Level */
|
||||
u8 tcrt; /* 0x10 - Critical Threshold */
|
||||
u8 tpsv; /* 0x11 - Passive Threshold */
|
||||
u8 tmax; /* 0x12 - CPU Tj_max */
|
||||
u8 tpmp; /* 0x13 - TPM Present */
|
||||
u8 s5u0; /* 0x14 - Enable USB in S5 */
|
||||
u8 s3u0; /* 0x15 - Enable USB in S3 */
|
||||
u8 s33g; /* 0x16 - Enable 3G in S3 */
|
||||
u8 lids; /* 0x17 - LID State */
|
||||
u8 pwrs; /* 0x18 - AC Power State */
|
||||
u32 cmem; /* 0x19 - 0x1c - CBMEM TOC */
|
||||
u32 cbmc; /* 0x1d - 0x20 - Coreboot Memory Console */
|
||||
u32 pm1i; /* 0x21 - 0x24 - PM1 wake status bit */
|
||||
u8 rsvd3[219];
|
||||
|
||||
/* ChromeOS specific (starts at 0x100)*/
|
||||
/* ChromeOS specific (0x100 - 0xfff) */
|
||||
chromeos_acpi_t chromeos;
|
||||
|
||||
/* Device specific (0x1000) */
|
||||
device_nvs_t dev;
|
||||
} __attribute__((packed)) global_nvs_t;
|
||||
|
||||
#ifdef __SMM__
|
||||
/* Used in SMM to find the ACPI GNVS address */
|
||||
global_nvs_t *smm_get_gnvs(void);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue