tegra124: clean-ups for SPI driver
This addresses comments made in the first round of code reviews for the SPI driver and does a few minor clean-up tasks. It also adds better error handling in tegra_spi_cbfs_read() for the first transfer (sending the read command and address). BUG=none BRANCH=none TEST=built and booted on nyan Change-Id: I8ee85a6e815e4a65a6e3beb4fb51d7660bed2ff8 Reviewed-on: https://chromium-review.googlesource.com/173599 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: David James <davidjames@chromium.org>
This commit is contained in:
David Hendricks
chrome-internal-fetch
parent
d706bb70f4
commit
1e2f9fd442
2 changed files with 38 additions and 67 deletions
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@ -127,14 +127,19 @@ struct tegra_spi_regs {
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u32 rx_data; /* 0x01c: SPI_RX_DATA */
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u32 dma_ctl; /* 0x020: SPI_DMA_CTL */
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u32 dma_blk; /* 0x024: SPI_DMA_BLK */
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u8 rsvd[0xe0]; /* 0x028-0x107: reserved */
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u32 rsvd[56]; /* 0x028-0x107: reserved */
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u32 tx_fifo; /* 0x108: SPI_FIFO1 */
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u8 rsvd2[0x7c]; /* 0x10c-0x187 reserved */
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u32 rsvd2[31]; /* 0x10c-0x187 reserved */
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u32 rx_fifo; /* 0x188: SPI_FIFO2 */
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u32 spare_ctl; /* 0x18c: SPI_SPARE_CTRL */
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} __attribute__((packed));
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struct tegra_spi_channel tegra_spi_channels[TEGRA124_NUM_SPI_CHANNELS] = {
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struct tegra_spi_channel {
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struct spi_slave slave;
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struct tegra_spi_regs *regs;
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};
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static struct tegra_spi_channel tegra_spi_channels[] = {
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/*
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* Note: Tegra pinmux must be setup for corresponding SPI channel in
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* order for its registers to be accessible. If pinmux has not been
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@ -169,8 +174,13 @@ struct tegra_spi_channel tegra_spi_channels[TEGRA124_NUM_SPI_CHANNELS] = {
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},
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};
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void spi_init(void)
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static void flush_fifos(struct tegra_spi_regs *regs)
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{
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setbits_le32(®s->fifo_status, SPI_FIFO_STATUS_RX_FIFO_FLUSH |
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SPI_FIFO_STATUS_TX_FIFO_FLUSH);
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while (read32(®s->fifo_status) &
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(SPI_FIFO_STATUS_RX_FIFO_FLUSH | SPI_FIFO_STATUS_TX_FIFO_FLUSH))
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;
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}
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void tegra_spi_init(unsigned int bus)
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@ -190,39 +200,18 @@ void tegra_spi_init(unsigned int bus)
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SPI_CMD1_CS_SW_HW | SPI_CMD1_CS_SW_VAL);
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/* 8-bit transfers, unpacked mode, most significant bit first */
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clrbits_le32(®s->command1, SPI_CMD1_BIT_LEN_MASK | SPI_CMD1_PACKED);
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clrbits_le32(®s->command1,
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SPI_CMD1_BIT_LEN_MASK | SPI_CMD1_PACKED);
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setbits_le32(®s->command1, 7 << SPI_CMD1_BIT_LEN_SHIFT);
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/* flush FIFOs */
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setbits_le32(®s->fifo_status, SPI_FIFO_STATUS_RX_FIFO_FLUSH |
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SPI_FIFO_STATUS_TX_FIFO_FLUSH);
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while (read32(®s->fifo_status) &
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(SPI_FIFO_STATUS_RX_FIFO_FLUSH | SPI_FIFO_STATUS_TX_FIFO_FLUSH))
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;
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flush_fifos(regs);
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}
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printk(BIOS_INFO, "Tegra SPI bus %d initialized.\n", bus);
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}
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static struct tegra_spi_channel * const to_tegra_spi(int bus) {
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int i;
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struct tegra_spi_channel *channel = NULL;
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for (i = 0; i < ARRAY_SIZE(tegra_spi_channels); i++) {
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if (tegra_spi_channels[i].slave.bus == bus)
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channel = &tegra_spi_channels[i];
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}
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return channel;
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}
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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if (cs < 0 || cs > 3)
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return 0;
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if (!to_tegra_spi(bus))
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return 0;
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return 1;
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return &tegra_spi_channels[bus - 1];
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}
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void spi_cs_activate(struct spi_slave *slave)
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@ -264,19 +253,19 @@ static void print_fifo_status(struct tegra_spi_channel *spi)
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{
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u32 status = read32(&spi->regs->fifo_status);
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printk(BIOS_DEBUG, "Raw FIFO status: 0x%08x\n", status);
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printk(BIOS_INFO, "Raw FIFO status: 0x%08x\n", status);
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if (status & SPI_FIFO_STATUS_TX_FIFO_OVF)
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printk(BIOS_DEBUG, "\tTx overflow detected\n");
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printk(BIOS_INFO, "\tTx overflow detected\n");
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if (status & SPI_FIFO_STATUS_TX_FIFO_UNR)
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printk(BIOS_DEBUG, "\tTx underrun detected\n");
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printk(BIOS_INFO, "\tTx underrun detected\n");
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if (status & SPI_FIFO_STATUS_RX_FIFO_OVF)
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printk(BIOS_DEBUG, "\tRx overflow detected\n");
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printk(BIOS_INFO, "\tRx overflow detected\n");
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if (status & SPI_FIFO_STATUS_RX_FIFO_UNR)
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printk(BIOS_DEBUG, "\tRx underrun detected\n");
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printk(BIOS_INFO, "\tRx underrun detected\n");
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printk(BIOS_DEBUG, "TX_FIFO: 0x%08x, TX_DATA: 0x%08x\n",
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printk(BIOS_INFO, "TX_FIFO: 0x%08x, TX_DATA: 0x%08x\n",
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read32(&spi->regs->tx_fifo), read32(&spi->regs->tx_data));
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printk(BIOS_DEBUG, "RX_FIFO: 0x%08x, RX_DATA: 0x%08x\n",
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printk(BIOS_INFO, "RX_FIFO: 0x%08x, RX_DATA: 0x%08x\n",
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read32(&spi->regs->rx_fifo), read32(&spi->regs->rx_data));
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}
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@ -293,8 +282,8 @@ static void clear_fifo_status(struct tegra_spi_channel *spi)
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static void dump_regs(struct tegra_spi_channel *spi,
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struct apb_dma_channel *dma)
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{
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printk(BIOS_DEBUG, "DMA regs:\n");
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printk(BIOS_DEBUG, "\tahb_ptr: 0x%08x\n"
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printk(BIOS_INFO, "DMA regs:\n"
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"\tahb_ptr: 0x%08x\n"
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"\tapb_ptr: 0x%08x\n"
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"\tahb_seq: 0x%08x\n"
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"\tapb_seq: 0x%08x\n"
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@ -312,8 +301,8 @@ static void dump_regs(struct tegra_spi_channel *spi,
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read32(&dma->regs->wcount),
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read32(&dma->regs->dma_byte_sta),
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read32(&dma->regs->word_transfer));
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printk(BIOS_DEBUG, "SPI regs:\n");
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printk(BIOS_DEBUG, "\tdma_blk: 0x%08x\n"
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printk(BIOS_INFO, "SPI regs:\n"
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"\tdma_blk: 0x%08x\n"
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"\tcommand1: 0x%08x\n"
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"\tdma_ctl: 0x%08x\n"
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"\ttrans_status: 0x%08x\n",
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@ -334,7 +323,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bitsout,
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ASSERT(bitsout % 8 == 0 && bitsin % 8 == 0);
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/* tegra bus numbers start at 1 */
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ASSERT(slave->bus >= 1 && slave->bus <= TEGRA124_NUM_SPI_CHANNELS);
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ASSERT(slave->bus >= 1 && slave->bus <= ARRAY_SIZE(tegra_spi_channels));
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dma = dma_claim();
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if (!dma) {
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@ -342,14 +331,8 @@ int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bitsout,
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return -1;
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}
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/* flush FIFOs */
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setbits_le32(&spi->regs->fifo_status, SPI_FIFO_STATUS_RX_FIFO_FLUSH |
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SPI_FIFO_STATUS_TX_FIFO_FLUSH);
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while (read32(&spi->regs->fifo_status) & (SPI_FIFO_STATUS_RX_FIFO_FLUSH |
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SPI_FIFO_STATUS_TX_FIFO_FLUSH))
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;
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flush_fifos(spi->regs);
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/* A few common parameters used for both transmit and receive */
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/* APB bus width = 8-bits, address wrap for each word */
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clrbits_le32(&dma->regs->apb_seq, 0x7 << 28);
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/* AHB 1 word burst, bus width = 32 bits (fixed in hardware),
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@ -435,7 +418,8 @@ int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bitsout,
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/* set DMA bit in SPI_DMA_CTL to start */
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setbits_le32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA);
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/* start APBDMA after SPI DMA so we don't read empty bytes from Rx FIFO */
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/* start APBDMA after SPI DMA so we don't read empty bytes
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* from Rx FIFO */
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dma_start(dma);
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/* FIXME: delay loops should be "thread" friendly */
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@ -525,8 +509,12 @@ static size_t tegra_spi_cbfs_read(struct cbfs_media *media, void *dest,
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spi_cs_activate(spi->slave);
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if (spi_xfer(spi->slave, spi_read_cmd,
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sizeof(spi_read_cmd) * 8, NULL, 0) < 0)
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sizeof(spi_read_cmd) * 8, NULL, 0) < 0) {
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ret = -1;
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printk(BIOS_ERR, "SPI failed to transfer %u bytes\n",
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sizeof(spi_read_cmd));
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goto tegra_spi_cbfs_read_exit;
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}
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while (count > 0) {
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unsigned int remaining;
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@ -18,23 +18,6 @@
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#define __NVIDIA_TEGRA124_SPI_H__
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#include <stddef.h>
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#include <spi-generic.h>
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struct tegra_spi_channel {
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struct spi_slave slave;
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struct tegra_spi_regs *regs;
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/*
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* max transfer size and dma_buf address will be set by
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* mainboard-specific code, depending on the requirements for
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* the device connected
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*/
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unsigned int max_transfer_size;
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void *dma_buf;
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};
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#define TEGRA124_NUM_SPI_CHANNELS 6
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extern struct tegra_spi_channel tegra_spi_channels[];
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struct cbfs_media;
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int initialize_tegra_spi_cbfs_media(struct cbfs_media *media,
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