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broadwell: SPI: Clean up romstage and ramstage code

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- Use PCH_DEV_LPC instead of special case for SMM code.
- Change RCBA macros to be SPIBAR macros
- Clean up include files

BUG=chrome-os-partner:28234
TEST=None

Change-Id: I7d846e9c1c4627aea08fb09f2e85f86a98ec61a9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199192
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2014-05-01 14:51:27 -07:00 • committed by chrome-internal-fetch
commit 28ffd71a41
2 changed files with 15 additions and 19 deletions
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24
src/soc/intel/broadwell/romstage/spi.c
View file

@ -22,7 +22,9 @@
#include <device/pci_ids.h>
#include <device/pci_def.h>
#include <delay.h>
#include "pch.h"
#include <broadwell/spi.h>
#include <broadwell/rcba.h>
#include <broadwell/romstage.h>
#define SPI_DELAY 10 /* 10us */
#define SPI_RETRY 200000 /* 2s */
@ -33,39 +35,39 @@ static int early_spi_read_block(u32 offset, u8 size, u8 *buffer)
u32 i;
/* Clear status bits */
RCBA16(SPIBAR_HSFS) |= SPIBAR_HSFS_AEL | SPIBAR_HSFS_FCERR |
SPIBAR16(SPIBAR_HSFS) |= SPIBAR_HSFS_AEL | SPIBAR_HSFS_FCERR |
SPIBAR_HSFS_FDONE;
if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) {
if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) {
printk(BIOS_ERR, "SPI ERROR: transaction in progress\n");
return -1;
}
/* Set flash address */
RCBA32(SPIBAR_FADDR) = offset;
SPIBAR32(SPIBAR_FADDR) = offset;
/* Setup read transaction */
RCBA16(SPIBAR_HSFC) = SPIBAR_HSFC_BYTE_COUNT(size) |
SPIBAR16(SPIBAR_HSFC) = SPIBAR_HSFC_BYTE_COUNT(size) |
SPIBAR_HSFC_CYCLE_READ;
/* Start transactinon */
RCBA16(SPIBAR_HSFC) |= SPIBAR_HSFC_GO;
SPIBAR16(SPIBAR_HSFC) |= SPIBAR_HSFC_GO;
/* Wait for completion */
for (i = 0; i < SPI_RETRY; i++) {
if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) {
if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) {
/* Cycle in progress, wait 1ms */
udelay(SPI_DELAY);
continue;
}
if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_AEL) {
if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_AEL) {
printk(BIOS_ERR, "SPI ERROR: Access Error\n");
return -1;
}
if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_FCERR) {
if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_FCERR) {
printk(BIOS_ERR, "SPI ERROR: Flash Cycle Error\n");
return -1;
}
@ -81,11 +83,11 @@ static int early_spi_read_block(u32 offset, u8 size, u8 *buffer)
for (i = 0; i < size; i+=sizeof(u32)) {
if (size-i >= 4) {
/* reading >= dword */
*ptr32++ = RCBA32(SPIBAR_FDATA(i/sizeof(u32)));
*ptr32++ = SPIBAR32(SPIBAR_FDATA(i/sizeof(u32)));
} else {
/* reading < dword */
u8 j, *ptr8 = (u8*)ptr32;
u32 temp = RCBA32(SPIBAR_FDATA(i/sizeof(u32)));
u32 temp = SPIBAR32(SPIBAR_FDATA(i/sizeof(u32)));
for (j = 0; j < (size-i); j++) {
*ptr8++ = temp & 0xff;
temp >>= 8;

10
src/soc/intel/broadwell/spi.c
View file

@ -27,8 +27,8 @@
#include <arch/io.h>
#include <console/console.h>
#include <device/pci_ids.h>
#include <spi-generic.h>
#include <broadwell/pci_devs.h>
#define min(a, b) ((a)<(b)?(a):(b))
@ -286,15 +286,9 @@ void spi_init(void)
uint8_t *rcrb; /* Root Complex Register Block */
uint32_t rcba; /* Root Complex Base Address */
uint8_t bios_cntl;
device_t dev;
device_t dev = PCH_DEV_LPC;
ich9_spi_regs *ich9_spi;
#ifdef __SMM__
dev = PCI_DEV(0, 31, 0);
#else
dev = dev_find_slot(0, PCI_DEVFN(31, 0));
#endif
pci_read_config_dword(dev, 0xf0, &rcba);
/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
rcrb = (uint8_t *)(rcba & 0xffffc000);