tegra124: Clean up some #defines for DMA
This shortens the grostesquely huge APBDMACHAN_* defines by removing unecessary prefixes. Names of fields which appeared at the end of these huge #defines are preserved as they are presented in the manual, so searching for them is still easy. The goal is to make it so that we can actually use the #defines without the code becoming a hideous, line-broken mess. As they were, the #defines made code so ugly that it actually became less readable. Additionally, a couple trivial issues were found and fixed: - Removes duplicate AHB bus width #defines - Removes a non-sensical #define that seems to be a result of an incompleted copy+paste job. BUG=none BRANCH=none TEST=built and booted on Nyan Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I72195ff08ef51bb645a1e1ae5a11346998a12635 Reviewed-on: https://chromium-review.googlesource.com/175631 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org>
This commit is contained in:
David Hendricks
chrome-internal-fetch
parent
b8eb6ab4cd
commit
1a0a900f2d
3 changed files with 62 additions and 64 deletions
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@ -73,7 +73,7 @@ int dma_busy(struct apb_dma_channel * const channel)
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* as the channel is enabled. So for this function we'll use the
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* DMA_ACTIVITY bit.
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*/
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return read32(&channel->regs->sta) & APBDMACHAN_STA_DMA_ACTIVITY ? 1 : 0;
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return read32(&channel->regs->sta) & APB_STA_DMA_ACTIVITY ? 1 : 0;
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}
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/* claim a DMA channel */
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struct apb_dma_channel * const dma_claim(void)
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@ -85,7 +85,7 @@ struct apb_dma_channel * const dma_claim(void)
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* Set global enable bit, otherwise register access to channel
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* DMA registers will not be possible.
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*/
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setbits_le32(&apb_dma->command, APBDMA_COMMAND_GEN);
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setbits_le32(&apb_dma->command, APB_COMMAND_GEN);
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for (i = 0; i < ARRAY_SIZE(apb_dma_channels); i++) {
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regs = apb_dma_channels[i].regs;
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@ -125,7 +125,7 @@ void dma_release(struct apb_dma_channel * const channel)
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return;
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}
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clrbits_le32(&apb_dma->command, APBDMA_COMMAND_GEN);
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clrbits_le32(&apb_dma->command, APB_COMMAND_GEN);
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}
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int dma_start(struct apb_dma_channel * const channel)
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@ -133,7 +133,7 @@ int dma_start(struct apb_dma_channel * const channel)
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struct apb_dma_channel_regs *regs = channel->regs;
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/* Set ENB bit for this channel */
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setbits_le32(®s->csr, APBDMACHAN_CSR_ENB);
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setbits_le32(®s->csr, APB_CSR_ENB);
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return 0;
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}
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@ -143,7 +143,7 @@ int dma_stop(struct apb_dma_channel * const channel)
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struct apb_dma_channel_regs *regs = channel->regs;
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/* Clear ENB bit for this channel */
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clrbits_le32(®s->csr, APBDMACHAN_CSR_ENB);
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clrbits_le32(®s->csr, APB_CSR_ENB);
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return 0;
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}
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@ -33,20 +33,20 @@
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* bit controls or represents the status for the corresponding channel.
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* So we will not bother to list each individual bit in this case.
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*/
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#define APBDMA_COMMAND_GEN (1 << 31)
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#define APB_COMMAND_GEN (1 << 31)
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#define APBDMA_CNTRL_REG_COUNT_VALUE_MASK 0xffff
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#define APBDMA_CNTRL_REG_COUNT_VALUE_SHIFT 0
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#define APB_CNTRL_REG_COUNT_VALUE_MASK 0xffff
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#define APB_CNTRL_REG_COUNT_VALUE_SHIFT 0
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/*
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* Note: Many APB DMA controller registers are laid out such that each
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* bit controls or represents the status for the corresponding channel.
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* So we will not bother to list each individual bit in this case.
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*/
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#define APBDMA_COMMAND_GEN (1 << 31)
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#define APB_COMMAND_GEN (1 << 31)
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#define APBDMA_CNTRL_REG_COUNT_VALUE_MASK 0xffff
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#define APBDMA_CNTRL_REG_COUNT_VALUE_SHIFT 0
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#define APB_CNTRL_REG_COUNT_VALUE_MASK 0xffff
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#define APB_CNTRL_REG_COUNT_VALUE_SHIFT 0
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struct apb_dma {
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u32 command; /* 0x00 */
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u32 status; /* 0x04 */
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@ -75,14 +75,14 @@ struct apb_dma {
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* Naming in the doc included a superfluous _CHANNEL_n_ for
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* each entry and was left out for the sake of conciseness.
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*/
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#define APBDMACHAN_CSR_ENB (1 << 31)
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#define APBDMACHAN_CSR_IE_EOC (1 << 30)
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#define APBDMACHAN_CSR_HOLD (1 << 29)
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#define APBDMACHAN_CSR_DIR (1 << 28)
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#define APBDMACHAN_CSR_ONCE (1 << 27)
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#define APBDMACHAN_CSR_FLOW (1 << 21)
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#define APBDMACHAN_CSR_REQ_SEL_MASK 0x1f
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#define APBDMACHAN_CSR_REQ_SEL_SHIFT 16
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#define APB_CSR_ENB (1 << 31)
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#define APB_CSR_IE_EOC (1 << 30)
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#define APB_CSR_HOLD (1 << 29)
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#define APB_CSR_DIR (1 << 28)
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#define APB_CSR_ONCE (1 << 27)
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#define APB_CSR_FLOW (1 << 21)
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#define APB_CSR_REQ_SEL_MASK 0x1f
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#define APB_CSR_REQ_SEL_SHIFT 16
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enum apbdmachan_req_sel {
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APBDMA_SLAVE_CNTR_REQ = 0,
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@ -119,46 +119,41 @@ enum apbdmachan_req_sel {
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APBDMA_SLAVE_NA31 = 31,
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};
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#define APBDMACHAN_STA_BSY (1 << 31)
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#define APBDMACHAN_STA_ISE_EOC (1 << 30)
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#define APBDMACHAN_STA_HALT (1 << 29)
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#define APBDMACHAN_STA_PING_PONG_STA (1 << 28)
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#define APBDMACHAN_STA_DMA_ACTIVITY (1 << 27)
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#define APBDMACHAN_STA_CHANNEL_PAUSE (1 << 26)
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#define APB_STA_BSY (1 << 31)
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#define APB_STA_ISE_EOC (1 << 30)
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#define APB_STA_HALT (1 << 29)
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#define APB_STA_PING_PONG_STA (1 << 28)
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#define APB_STA_DMA_ACTIVITY (1 << 27)
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#define APB_STA_CHANNEL_PAUSE (1 << 26)
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#define APBDMACHAN_CSRE_CHANNEL_PAUSE (1 << 31)
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#define APBDMACHAN_CSRE_TRIG_SEL_MASK 0x3f
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#define APBDMACHAN_CSRE_TRIG_SEL_SHIFT 14
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#define APB_CSRE_CHANNEL_PAUSE (1 << 31)
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#define APB_CSRE_TRIG_SEL_MASK 0x3f
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#define APB_CSRE_TRIG_SEL_SHIFT 14
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#define APBDMACHAN_AHB_PTR_MASK (0x3fffffff)
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#define APBDMACHAN_AHB_PTR_SHIFT 2
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#define AHB_PTR_MASK (0x3fffffff)
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#define AHB_PTR_SHIFT 2
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#define APBDMACHAN_AHB_SEQ_INTR_ENB (1 << 31)
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#define APBDMACHAN_AHB_SEQ_AHB_BUS_WIDTH_MASK 0x7
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#define APBDMACHAN_AHB_SEQ_AHB_BUS_WIDTH_SHIFT 28
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#define APBDMACHAN_AHB_SEQ_AHB_DATA_SWAP (1 << 27)
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#define APBDMACHAN_AHB_SEQ_AHB_BURST_MASK 0x7
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#define APBDMACHAN_AHB_SEQ_AHB_BURST_SHIFT 24
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#define APBDMACHAN_AHB_SEQ_DBL_BUF (1 << 19)
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#define APBDMACHAN_AHB_SEQ_WRAP_MASK 0x7
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#define APBDMACHAN_AHB_SEQ_WRAP_SHIFT 16
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#define AHB_SEQ_INTR_ENB (1 << 31)
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#define AHB_BUS_WIDTH_MASK 0x7
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#define AHB_BUS_WIDTH_SHIFT 28
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#define AHB_DATA_SWAP (1 << 27)
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#define AHB_BURST_MASK 0x7
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#define AHB_BURST_SHIFT 24
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#define AHB_SEQ_DBL_BUF (1 << 19)
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#define AHB_SEQ_WRAP_MASK 0x7
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#define AHB_SEQ_WRAP_SHIFT 16
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#define APBDMACHAN_AHB_SEQ_AHB_BUS_WIDTH_MASK 0x7
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#define APBDMACHAN_AHB_SEQ_AHB_BUS_WIDTH_SHIFT 28
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#define APB_PTR_MASK 0x3fffffff
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#define APB_PTR_SHIFT 2
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#define APBDMACHAN_APB_PTR_MASK 0x3fffffff
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#define APBDMACHAN_APB_PTR_SHIFT 2
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#define APB_BUS_WIDTH_MASK 0x7
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#define APB_BUS_WIDTH_SHIFT 28
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#define APB_DATA_SWAP (1 << 27)
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#define APB_ADDR_WRAP_MASK 0x7
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#define APB_ADDR_WRAP_SHIFT 16
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#define APBDMACHAN_APB_SEQ_APB_BUS_WIDTH_MASK 0x7
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#define APBDMACHAN_APB_SEQ_APB_BUS_WIDTH_SHIFT 28
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#define APBDMACHAN_APB_SEQ_APB_DATA_SWAP (1 << 27)
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#define APBDMACHAN_APB_SEQ_APB_ADDR_WRAP_MASK 0x7
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#define APBDMACHAN_APB_SEQ_APB_ADDR_WRAP_SHIFT 16
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#define APBDMACHAN_WORD_TRANSFER_
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#define APBDMACHAN_WORD_TRANSFER_MASK 0x0fffffff
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#define APBDMACHAN_WORD_TRANSFER_SHIFT 2
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#define APB_WORD_TRANSFER_MASK 0x0fffffff
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#define APB_WORD_TRANSFER_SHIFT 2
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struct apb_dma_channel_regs {
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u32 csr; /* 0x00 */
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@ -408,13 +408,16 @@ static void setup_dma_params(struct tegra_spi_channel *spi,
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struct apb_dma_channel *dma)
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{
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/* APB bus width = 8-bits, address wrap for each word */
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clrbits_le32(&dma->regs->apb_seq, 0x7 << 28);
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clrbits_le32(&dma->regs->apb_seq,
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AHB_BUS_WIDTH_MASK << AHB_BUS_WIDTH_SHIFT);
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/* AHB 1 word burst, bus width = 32 bits (fixed in hardware),
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* no address wrapping */
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clrsetbits_le32(&dma->regs->ahb_seq,
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(0x7 << 24) | (0x7 << 16), 0x4 << 24);
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(AHB_BURST_MASK << AHB_BURST_SHIFT) |
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(AHB_SEQ_WRAP_MASK << AHB_SEQ_WRAP_SHIFT),
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AHB_BURST_MASK << AHB_BURST_SHIFT);
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/* Set ONCE mode to transfer one "blocK" at a time (64KB). */
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setbits_le32(&dma->regs->csr, 1 << 27);
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setbits_le32(&dma->regs->csr, APB_CSR_ONCE);
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}
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static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi,
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@ -447,7 +450,7 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi,
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write32((u32)&spi->regs->tx_fifo, &spi->dma_out->regs->apb_ptr);
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write32((u32)spi->out_buf, &spi->dma_out->regs->ahb_ptr);
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setbits_le32(&spi->dma_out->regs->csr, APBDMACHAN_CSR_DIR);
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setbits_le32(&spi->dma_out->regs->csr, APB_CSR_DIR);
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setup_dma_params(spi, spi->dma_out);
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write32(wcount, &spi->dma_out->regs->wcount);
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} else {
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@ -460,7 +463,7 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi,
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write32((u32)&spi->regs->rx_fifo, &spi->dma_in->regs->apb_ptr);
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write32((u32)spi->in_buf, &spi->dma_in->regs->ahb_ptr);
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clrbits_le32(&spi->dma_in->regs->csr, APBDMACHAN_CSR_DIR);
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clrbits_le32(&spi->dma_in->regs->csr, APB_CSR_DIR);
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setup_dma_params(spi, spi->dma_in);
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write32(wcount, &spi->dma_in->regs->wcount);
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}
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