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baytrail: Set SOC power budget values for SdpProfile 2&3

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These values are for the 2 and 4 core B-step parts.

BUG=chrome-os-partner:17279
BRANCH=baytrail
TEST=boot on rambi and check for valid GPU power values from DPTF

Change-Id: I2772cb9dbf17560fc31f871a111f32131c7e5105
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183101
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 701273892c7bdaf898a94a337fae9f7373a9c748)
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183102
This commit is contained in:
Duncan Laurie 2014-01-17 13:22:02 -08:00 • committed by chrome-internal-fetch
commit 87d49323ca
2 changed files with 3 additions and 3 deletions
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4
src/soc/intel/baytrail/dptf.c
View file

@ -37,8 +37,8 @@ static const struct reg_script dptf_init_settings[] = {
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_XXPROCHOT, 0x00061029),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_SLM0, 0x00001029),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_SLM1, 0x00001029),
/* ratio 10 = 1333mhz for 2.5W fanless */
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_SOC_POWER_BUDGET, 0x00000A00),
/* ratio 11 = 1466mhz for mid and entry celeron */
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_SOC_POWER_BUDGET, 0x00000B00),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_SOC_ENERGY_CREDIT, 0x00000002),
REG_SCRIPT_END,
};

2
src/soc/intel/baytrail/gfx.c
View file

@ -142,7 +142,7 @@ static const struct reg_script gfx_init_script[] = {
/* Program PUNIT_GPU_EC_VIRUS based on DPTF SDP */
/* SDP Profile 4 == 0x11940, others 0xcf08 */
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GPU_EC_VIRUS, 0x11940),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GPU_EC_VIRUS, 0xcf08),
/* GfxPause */
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00071388),