broadwell: pch.h: split USB into new headers
Move the XHCI and EHCI related register/bit defines into a separate header file at broadwell/ehci.h and broadwell/xhci.h BUG=chrome-os-partner:28234 TEST=None Change-Id: I24df90c797ebdc5dee1fe84ed57c565c5360dd1c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198554 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
chrome-internal-fetch
parent
9c97532460
commit
86ef1a45a2
3 changed files with 93 additions and 50 deletions
32
src/soc/intel/broadwell/broadwell/ehci.h
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32
src/soc/intel/broadwell/broadwell/ehci.h
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@ -0,0 +1,32 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef _BROADWELL_EHCI_H_
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#define _BROADWELL_EHCI_H_
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/* EHCI Memory Registers */
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#define EHCI_USB_CMD 0x20
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#define EHCI_USB_CMD_RUN (1 << 0)
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#define EHCI_USB_CMD_PSE (1 << 4)
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#define EHCI_USB_CMD_ASE (1 << 5)
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#define EHCI_PORTSC(port) (0x64 + (port * 4))
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#define EHCI_PORTSC_ENABLED (1 << 2)
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#define EHCI_PORTSC_SUSPEND (1 << 7)
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#endif
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@ -89,10 +89,6 @@
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#if defined (__SMM__) && !defined(__ASSEMBLER__)
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void intel_pch_finalize_smm(void);
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void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ);
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void usb_ehci_disable(device_t dev);
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void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ);
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void usb_xhci_route_all(void);
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#endif
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#if !defined(__ASSEMBLER__)
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@ -162,52 +158,6 @@ void pch_enable_lpc(void);
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#define PCH_ME_DEV PCI_DEV(0, 0x16, 0)
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#define PCH_PCIE_DEV_SLOT 28
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/* EHCI PCI Registers */
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#define EHCI_PWR_CTL_STS 0x54
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#define PWR_CTL_SET_MASK 0x3
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#define PWR_CTL_SET_D0 0x0
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#define PWR_CTL_SET_D3 0x3
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#define PWR_CTL_ENABLE_PME (1 << 8)
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#define PWR_CTL_STATUS_PME (1 << 15)
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/* EHCI Memory Registers */
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#define EHCI_USB_CMD 0x20
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#define EHCI_USB_CMD_RUN (1 << 0)
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#define EHCI_USB_CMD_PSE (1 << 4)
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#define EHCI_USB_CMD_ASE (1 << 5)
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#define EHCI_PORTSC(port) (0x64 + (port * 4))
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#define EHCI_PORTSC_ENABLED (1 << 2)
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#define EHCI_PORTSC_SUSPEND (1 << 7)
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/* XHCI PCI Registers */
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#define XHCI_PWR_CTL_STS 0x74
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#define XHCI_USB2PR 0xd0
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#define XHCI_USB2PRM 0xd4
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#define XHCI_USB2PR_HCSEL 0x7fff
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#define XHCI_USB3PR 0xd8
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#define XHCI_USB3PR_SSEN 0x3f
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#define XHCI_USB3PRM 0xdc
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#define XHCI_USB3FUS 0xe0
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#define XHCI_USB3FUS_SS_MASK 3
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#define XHCI_USB3FUS_SS_SHIFT 3
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#define XHCI_USB3PDO 0xe8
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/* XHCI Memory Registers */
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#define XHCI_USB3_PORTSC(port) ((pch_is_lp() ? 0x510 : 0x570) + (port * 0x10))
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#define XHCI_USB3_PORTSC_CHST (0x7f << 17)
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#define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */
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#define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */
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#define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */
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#define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */
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#define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */
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#define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */
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#define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */
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#define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */
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#define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */
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#define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */
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#define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */
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#define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */
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/* PCI Configuration Space (D31:F3): SMBus */
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#define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3)
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#define SMB_BASE 0x20
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61
src/soc/intel/broadwell/broadwell/xhci.h
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61
src/soc/intel/broadwell/broadwell/xhci.h
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@ -0,0 +1,61 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef _BROADWELL_XHCI_H_
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#define _BROADWELL_XHCI_H_
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/* XHCI PCI Registers */
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#define XHCI_PWR_CTL_STS 0x74
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#define XHCI_PWR_CTL_SET_MASK 0x3
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#define XHCI_PWR_CTL_SET_D0 0x0
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#define XHCI_PWR_CTL_SET_D3 0x3
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#define XHCI_PWR_CTL_ENABLE_PME (1 << 8)
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#define XHCI_PWR_CTL_STATUS_PME (1 << 15)
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#define XHCI_USB2PR 0xd0
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#define XHCI_USB2PRM 0xd4
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#define XHCI_USB2PR_HCSEL 0x7fff
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#define XHCI_USB3PR 0xd8
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#define XHCI_USB3PR_SSEN 0x3f
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#define XHCI_USB3PRM 0xdc
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#define XHCI_USB3FUS 0xe0
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#define XHCI_USB3FUS_SS_MASK 3
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#define XHCI_USB3FUS_SS_SHIFT 3
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#define XHCI_USB3PDO 0xe8
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/* XHCI Memory Registers */
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#define XHCI_USB3_PORTSC(port) (0x510 + (port * 0x10))
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#define XHCI_USB3_PORTSC_CHST (0x7f << 17)
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#define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */
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#define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */
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#define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */
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#define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */
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#define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */
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#define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */
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#define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */
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#define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */
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#define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */
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#define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */
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#define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */
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#define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */
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#ifdef __SMM__
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void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ);
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#endif
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#endif
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