Tegra124: nyan: Disable VPR

On Tegra1x4 platforms, certain display-related registers
cannot be accessed unless the VPR registers are correctly
set up first. This allows the kernel graphics driver to
talk to the HW in the same manner on all Tegra SoCs.

Change-Id: I96e0c4075709da51be530a473da8d593ca498722
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/179327
Reviewed-by: Ronald Minnich <rminnich@chromium.org>

src/mainboard/google/nyan/mainboard.c

@@ -25,6 +25,7 @@
 #include <soc/nvidia/tegra/i2c.h>
 #include <soc/nvidia/tegra124/clk_rst.h>
 #include <soc/nvidia/tegra124/gpio.h>
+#include <soc/nvidia/tegra124/mc.h>
 #include <soc/nvidia/tegra124/pmc.h>
 #include <soc/nvidia/tegra124/spi.h>
 #include <soc/nvidia/tegra124/usb.h>
@@ -211,6 +212,12 @@ static void setup_kernel_info(void)
 	// value defined in BCT.
 	struct tegra_pmc_regs *pmc = (void*)TEGRA_PMC_BASE;
 	writel(0x80080000, &pmc->odmdata);
+
+	// Not strictly info, but kernel graphics driver needs this region locked down
+	struct tegra_mc_regs *mc = (void *)TEGRA_MC_BASE;
+	writel(0, &mc->mc_vpr_bom);
+	writel(0, &mc->mc_vpr_size);
+	writel(1, &mc->mc_vpr_ctrl);
 }
 
 static void setup_ec_spi(void)

src/soc/nvidia/tegra124/include/soc/addressmap.h

@@ -68,6 +68,7 @@ enum {
 	TEGRA_PMC_BASE =		TEGRA_APB_MISC_BASE + 0xE400,
 	TEGRA_EMC_BASE =		TEGRA_APB_MISC_BASE + 0xF400,
 	TEGRA_FUSE_BASE =		TEGRA_APB_MISC_BASE + 0xF800,
+	TEGRA_MC_BASE =			0x70019000,
 	TEGRA_CSITE_BASE =		0x70040000,
 	TEGRA_SYSCTR0_BASE =		0x700F0000,
 	TEGRA_USBD_BASE =		0x7D000000,

src/soc/nvidia/tegra124/mc.h

@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2010 - 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA124_MC_H_
+#define _TEGRA124_MC_H_
+
+#include <stdint.h>
+
+// Memory Controller registers we need/care about
+
+struct tegra_mc_regs {
+	u32 reserved0[4];
+	u32 mc_smmu_config;
+	u32 mc_smmu_tlb_config;
+	u32 mc_smmu_ptc_config;
+	u32 mc_smmu_ptb_asid;
+	u32 mc_smmu_ptb_data;
+	u32 reserved1[3];
+	u32 mc_smmu_tlb_flush;
+	u32 mc_smmu_ptc_flush;
+	u32 reserved2[6];
+	u32 mc_emem_cfg;
+	u32 mc_emem_adr_cfg;
+	u32 mc_emem_adr_cfg_dev0;
+	u32 mc_emem_adr_cfg_dev1;
+	u32 reserved3[12];
+	u32 mc_emem_arb_reserved[28];
+	u32 reserved4[338];
+	u32 mc_vpr_bom;
+	u32 mc_vpr_size;
+	u32 mc_vpr_ctrl;
+};
+
+#endif	/* _TEGRA124_MC_H_ */