erebion/coreboot
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Set the EC SPI clock source to PLLP and divide down to around 5MHz

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BUG=None
TEST=Built and booted into depthcharge. Saw that the AP could communicate with
the EC over SPI.
BRANCH=None

Change-Id: Ib19a8e543a96a0614a97afc6e795496b1bdfc8b4
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/173954
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
This commit is contained in:
Gabe Black 2013-10-22 06:01:30 -07:00 • committed by chrome-internal-fetch
commit c0e22d76d3
1 changed files with 2 additions and 0 deletions
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2
src/mainboard/google/nyan/bootblock.c
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@ -43,6 +43,8 @@ static void set_clock_sources(void)
clock_configure_source(i2c4, CLK_M, 1333);
clock_configure_source(i2c5, CLK_M, 1333);
clock_configure_source(sbc1, PLLP, 5000);
/* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
writel(PLLP << CLK_SOURCE_SHIFT, &clk_rst->clk_src_uarta);