tegra124: Add more PMC register details.

To initialize memory without BootROM, we need more details in the PMC registers,
including "io_dpd3_req", "por_dpd_ctrl", and various mask values.

BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan # successfully.

Change-Id: I5444e64f49a66320319a5c59ce14635364b74f39
Reviewed-on: https://chromium-review.googlesource.com/183231
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>

src/soc/nvidia/tegra124/pmc.h

@@ -62,10 +62,36 @@ struct tegra_pmc_regs {
 	u32 no_iopower;
 	u32 pwr_det;
 	u32 pwr_det_latch;
-	u32 scratch[20];
+	u32 scratch0;
+	u32 scratch1;
+	u32 scratch2;
+	u32 scratch3;
+	u32 scratch4;
+	u32 scratch5;
+	u32 scratch6;
+	u32 scratch7;
+	u32 scratch8;
+	u32 scratch9;
+	u32 scratch10;
+	u32 scratch11;
+	u32 scratch12;
+	u32 scratch13;
+	u32 scratch14;
+	u32 scratch15;
+	u32 scratch16;
+	u32 scratch17;
+	u32 scratch18;
+	u32 scratch19;
 	u32 odmdata;
-	u32 scratch21[24 - 21];
-	u32 secure_scratch[6];
+	u32 scratch21;
+	u32 scratch22;
+	u32 scratch23;
+	u32 secure_scratch0;
+	u32 secure_scratch1;
+	u32 secure_scratch2;
+	u32 secure_scratch3;
+	u32 secure_scratch4;
+	u32 secure_scratch5;
 	u32 cpupwrgood_timer;
 	u32 cpupwroff_timer;
 	u32 pg_mask;
@@ -79,7 +105,25 @@ struct tegra_pmc_regs {
 	u32 usb_a0;
 	u32 crypto_op;
 	u32 pllp_wb0_override;
-	u32 scratch24[43 - 24];
+	u32 scratch24;
+	u32 scratch25;
+	u32 scratch26;
+	u32 scratch27;
+	u32 scratch28;
+	u32 scratch29;
+	u32 scratch30;
+	u32 scratch31;
+	u32 scratch32;
+	u32 scratch33;
+	u32 scratch34;
+	u32 scratch35;
+	u32 scratch36;
+	u32 scratch37;
+	u32 scratch38;
+	u32 scratch39;
+	u32 scratch40;
+	u32 scratch41;
+	u32 scratch42;
 	u32 bondout_mirror[3];
 	u32 sys_33v_en;
 	u32 bondout_mirror_access;
@@ -124,9 +168,24 @@ struct tegra_pmc_regs {
 	u32 utmip_uhsic_status;
 	u32 utmip_uhsic_fake;
 	u32 bondout_mirror3[5 - 3];
-	u32 secure_scratch6[8 - 6];
-	u32 scratch43[56 - 43];
-	u32 scratch_eco[3];
+	u32 secure_scratch6;
+	u32 secure_scratch7;
+	u32 scratch43;
+	u32 scratch44;
+	u32 scratch45;
+	u32 scratch46;
+	u32 scratch47;
+	u32 scratch48;
+	u32 scratch49;
+	u32 scratch50;
+	u32 scratch51;
+	u32 scratch52;
+	u32 scratch53;
+	u32 scratch54;
+	u32 scratch55;
+	u32 scratch0_eco;
+	u32 por_dpd_ctrl;
+	u32 scratch2_eco;
 	u32 utmip_uhsic_line_wakeup;
 	u32 utmip_bias_master_cntrl;
 	u32 utmip_master_config;
@@ -153,10 +212,106 @@ struct tegra_pmc_regs {
 	u32 reg_short;
 	u32 pg_mask_andor;
 	u8 _rsv1[0x2c];
-	u32 secure_scratch8[24 - 8];
-	u32 scratch56[120 - 56];
+	u32 secure_scratch8;
+	u32 secure_scratch9;
+	u32 secure_scratch10;
+	u32 secure_scratch11;
+	u32 secure_scratch12;
+	u32 secure_scratch13;
+	u32 secure_scratch14;
+	u32 secure_scratch15;
+	u32 secure_scratch16;
+	u32 secure_scratch17;
+	u32 secure_scratch18;
+	u32 secure_scratch19;
+	u32 secure_scratch20;
+	u32 secure_scratch21;
+	u32 secure_scratch22;
+	u32 secure_scratch23;
+	u32 secure_scratch24;
+	u32 secure_scratch25;
+	u32 secure_scratch26;
+	u32 secure_scratch27;
+	u32 secure_scratch28;
+	u32 secure_scratch29;
+	u32 secure_scratch30;
+	u32 secure_scratch31;
+	u32 secure_scratch32;
+	u32 secure_scratch33;
+	u32 secure_scratch34;
+	u32 secure_scratch35;
+	u8 _rsv2[0xd0];
+	u32 cntrl2;
+	u8 _rsv3[0x18];
+	u32 io_dpd3_req;
+	u8 _rsv4[0x1a0];
+	u32 scratch56;
+	u32 scratch57;
+	u32 scratch58;
+	u32 scratch59;
+	u32 scratch60;
+	u32 scratch61;
+	u32 scratch62;
+	u32 scratch63;
+	u32 scratch64;
+	u32 scratch65;
+	u32 scratch66;
+	u32 scratch67;
+	u32 scratch68;
+	u32 scratch69;
+	u32 scratch70;
+	u32 scratch71;
+	u32 scratch72;
+	u32 scratch73;
+	u32 scratch74;
+	u32 scratch75;
+	u32 scratch76;
+	u32 scratch77;
+	u32 scratch78;
+	u32 scratch79;
+	u32 scratch80;
+	u32 scratch81;
+	u32 scratch82;
+	u32 scratch83;
+	u32 scratch84;
+	u32 scratch85;
+	u32 scratch86;
+	u32 scratch87;
+	u32 scratch88;
+	u32 scratch89;
+	u32 scratch90;
+	u32 scratch91;
+	u32 scratch92;
+	u32 scratch93;
+	u32 scratch94;
+	u32 scratch95;
+	u32 scratch96;
+	u32 scratch97;
+	u32 scratch98;
+	u32 scratch99;
+	u32 scratch100;
+	u32 scratch101;
+	u32 scratch102;
+	u32 scratch103;
+	u32 scratch104;
+	u32 scratch105;
+	u32 scratch106;
+	u32 scratch107;
+	u32 scratch108;
+	u32 scratch109;
+	u32 scratch110;
+	u32 scratch111;
+	u32 scratch112;
+	u32 scratch113;
+	u32 scratch114;
+	u32 scratch115;
+	u32 scratch116;
+	u32 scratch117;
+	u32 scratch118;
+	u32 scratch119;
 };
-check_member(tegra_pmc_regs, scratch56, 0x340);
+
+check_member(tegra_pmc_regs, scratch119, 0x6fc);
 
 enum {
 	PMC_PWRGATE_TOGGLE_PARTID_MASK = 0x1f,
@@ -190,6 +345,29 @@ enum {
 		0x3 << PMC_CNTRL_CPUPWRGOOD_SEL_SHIFT
 };
 
+enum {
+	PMC_DDR_PWR_EMMC_MASK = 1 << 1,
+	PMC_DDR_PWR_VAL_MASK = 1 << 0,
+};
+
+enum {
+	PMC_DDR_CFG_PKG_MASK = 1 << 0,
+	PMC_DDR_CFG_IF_MASK = 1 << 1,
+	PMC_DDR_CFG_XM0_RESET_TRI_MASK = 1 << 12,
+	PMC_DDR_CFG_XM0_RESET_DPDIO_MASK = 1 << 13,
+};
+
+enum {
+	PMC_NO_IOPOWER_MEM_MASK = 1 << 7,
+	PMC_NO_IOPOWER_MEM_COMP_MASK = 1 << 16,
+};
+
+enum {
+	PMC_POR_DPD_CTRL_MEM0_ADDR0_CLK_SEL_DPD_MASK = 1 << 0,
+	PMC_POR_DPD_CTRL_MEM0_ADDR1_CLK_SEL_DPD_MASK = 1 << 1,
+	PMC_POR_DPD_CTRL_MEM0_HOLD_CKE_LOW_OVR_MASK = 1 << 31,
+};
+
 enum {
 	PMC_CNTRL2_HOLD_CKE_LOW_EN = 0x1 << 12
 };