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broadwell: Add function to read WPSR from SPI

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Add a function to the romstage SPI code to read and return the
WPSR to determine the software write protect status at boot.

BUG=chrome-os-partner:28234
TEST=None

Change-Id: Ia68c02317ed1c2149fd9de1f60598b6f101d9686
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199190
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2014-05-01 14:39:28 -07:00 • committed by chrome-internal-fetch
commit 935404da11
2 changed files with 43 additions and 0 deletions
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9
src/soc/intel/broadwell/romstage/romstage.c
View file

@ -249,3 +249,12 @@ void ramstage_cache_invalid(struct ramstage_cache *cache)
#endif
}
#endif
#if CONFIG_CHROMEOS
int vboot_get_sw_write_protect(void)
{
u8 status;
/* Return unprotected status if status read fails. */
return (early_spi_read_wpsr(&status) ? 0 : !!(status & 0x80));
}
#endif

34
src/soc/intel/broadwell/romstage/spi.c
View file

@ -111,3 +111,37 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer)
return 0;
}
/*
* Minimal set of commands to read WPSR from SPI.
* Don't use this code outside romstage -- it trashes the opmenu table.
* Returns 0 on success, < 0 on failure.
*/
int early_spi_read_wpsr(u8 *sr)
{
int retry;
/* No address associated with rdsr */
SPIBAR8(SPIBAR_OPTYPE) = 0x0;
/* Setup opcode[0] = read wpsr */
SPIBAR8(SPIBAR_OPMENU_LOWER) = 0x5;
/* Start transaction */
SPIBAR16(SPIBAR_SSFC) = SPIBAR_SSFC_DATA | SPIBAR_SSFC_GO;
/* Wait for error / complete status */
for (retry = SPI_RETRY; retry; retry--) {
u16 status = SPIBAR16(SPIBAR_SSFS);
if (status & SPIBAR_SSFS_ERROR) {
printk(BIOS_ERR, "SPI rdsr failed\n");
return -1;
} else if (status & SPIBAR_SSFS_DONE) {
break;
}
udelay(SPI_DELAY);
}
*sr = SPIBAR32(SPIBAR_FDATA(0)) & 0xff;
return 0;
}