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tegra124 and nyan: fill in the devicetree a bit more, add defines

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Still working on getting it all, but this is a start.

BUG=None
TEST=Builds
BRANCH=None

Change-Id: I0e3eedd45bb056644a92c85405fde5f2ac748252
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/173684
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
This commit is contained in:
Ronald G. Minnich 2013-10-18 08:44:44 -07:00 • committed by chrome-internal-fetch
commit c107eaca3d
2 changed files with 29 additions and 0 deletions
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27
src/mainboard/google/nyan/devicetree.cb
View file

@ -19,7 +19,34 @@
chip soc/nvidia/tegra124
device cpu_cluster 0 on end
# N.B. We ae not using the device tree in an effective way.
# We need to change this in future such that the on-soc
# devices are 'chips', which will allow us to go at them
# in parallel. This is even easier on the ARM SOCs since there
# are no single-access resources such as the infamous
# cf8/cfc registers found on PCs.
register "display_controller" = "TEGRA_ARM_DISPLAYA"
register "xres" = "2560"
register "yres" = "1600"
register "framebuffer_bits_per_pixel" = "24"
register "cache_policy" = "DCACHE_WRITETHROUGH"
# still trying to find these, but they'll be left untouched
# since they are zero (for now).
register "backlight_en_gpio" = "GPIO(H2)"
register "lvds_shutdown_gpio" = "0"
register "backlight_vdd_gpio" = "0"
register "panel_vdd_gpio" = "GPIO(O4)"
register "pwm" = "-1"
# taken from u-boot; these look wrong however.
register "vdd_delay" = "400"
register "vdd_data_delay" = "4"
register "data_backlight_delay" = "203"
register "backlight_pwm_delay" = "17"
register "pwm_backlight_en_delay" = "15"
# we don't know any values save these at present.
register "href_to_sync" = "1"
register "vref_to_sync" = "1"
end

2
src/soc/nvidia/tegra124/include/soc/addressmap.h
View file

@ -28,6 +28,8 @@ enum {
enum {
TEGRA_ARM_PERIPHBASE = 0x50040000,
TEGRA_ARM_DISPLAYA = 0x54200000,
TEGRA_ARM_DISPLAYB = 0x54240000,
TEGRA_PG_UP_BASE = 0x60000000,
TEGRA_TMRUS_BASE = 0x60005010,
TEGRA_CLK_RST_BASE = 0x60006000,