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baytrail: lock down registers before handoff

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The following registers are locked before OS resume
handoff or payload handoff:

- SMI_LOCK - global SMI enable
- BILD - bios bootblock settings
- CF9 - cf9 reset settings
- BCR - control of SMI generation on BIOS writes

BUG=chrome-os-partner:24624
BRANCH=baytrail
TEST=Built and booted. S3 resume. Checked register settings.

Change-Id: I19758af6f2edaf78130dcf6cd5525cbfcbe6a261
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/185200
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Aaron Durbin 2014-02-06 10:21:24 -06:00 • committed by chrome-internal-fetch
commit 82cce4d2b4
2 changed files with 33 additions and 0 deletions
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4
src/soc/intel/baytrail/baytrail/lpc.h
View file

@ -47,4 +47,8 @@ enum baytrail_stepping {
STEP_C0,
};
/* Registers behind the RCBA_BASE_ADDRESS bar. */
#define GCS 0x00
# define BILD (1 << 0)
#endif /* _BAYTRAIL_LPC_H_ */

29
src/soc/intel/baytrail/southcluster.c
View file

@ -20,6 +20,7 @@
#include <stdint.h>
#include <arch/io.h>
#include <bootstate.h>
#include <cbmem.h>
#include <console/console.h>
#include <device/device.h>
@ -35,6 +36,7 @@
#include <baytrail/pci_devs.h>
#include <baytrail/pmc.h>
#include <baytrail/ramstage.h>
#include <baytrail/spi.h>
#include "chip.h"
static inline void
@ -419,3 +421,30 @@ static const struct pci_driver southcluster __pci_driver = {
.vendor = PCI_VENDOR_ID_INTEL,
.device = LPC_DEVID,
};
static void finalize_chipset(void *unused)
{
const unsigned long bcr = SPI_BASE_ADDRESS + BCR;
const unsigned long gcs = RCBA_BASE_ADDRESS + GCS;
const unsigned long gen_pmcon2 = PMC_BASE_ADDRESS + GEN_PMCON2;
const unsigned long etr = PMC_BASE_ADDRESS + ETR;
/* Set the lock enable on the BIOS control register. */
write32(bcr, read32(bcr) | BCR_LE);
/* Set BIOS lock down bit controlling boot block size and swapping. */
write32(gcs, read32(gcs) | BILD);
/* Lock sleep stretching policy and set SMI lock. */
write32(gen_pmcon2, read32(gen_pmcon2) | SLPSX_STR_POL_LOCK | SMI_LOCK);
/* Set the CF9 lock. */
write32(etr, read32(etr) | CF9LOCK);
}
BOOT_STATE_INIT_ENTRIES(finalize_bscb) = {
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY,
finalize_chipset, NULL),
BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT,
finalize_chipset, NULL),
};