nyan: change devicetree for the new display settings.
These panel numbers provided by the OEM. The old display will stop working. BUG=None TEST=builds. I'll test when I get a unit. BRANCH=None Change-Id: I6020f0c725d44c4b69d5806e0dfc8da125686baf Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/177958 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org>
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1 changed files with 16 additions and 11 deletions
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@ -26,8 +26,8 @@ chip soc/nvidia/tegra124
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# are no single-access resources such as the infamous
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# cf8/cfc registers found on PCs.
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register "display_controller" = "TEGRA_ARM_DISPLAYA"
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register "xres" = "2560"
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register "yres" = "1700"
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register "xres" = "1366"
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register "yres" = "768"
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# this setting is what nvidia does; it makes no sense
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# and does not agree with hardware. Why'd they do it?
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register "framebuffer_bits_per_pixel" = "24"
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@ -59,17 +59,22 @@ chip soc/nvidia/tegra124
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#V sync = 1713 - 1703 = 10
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#V back porch = 1749 - 1713 = 36
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#href_to_sync and vref_to_sync are from the vendor
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register "href_to_sync" = "11"
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register "hfront_porch" = "48"
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register "hsync_width" = "32"
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register "hback_porch" = "80"
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#this is just an example for a Pixel panel; other panels differ.
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# Here is a peppy panel:
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# 1366x768 (0x45) 76.4MHz -HSync -VSync *current +preferred
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# h: width 1366 start 1502 end 1532 total 1592
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# v: height 768 start 776 end 788 total 800
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# These numbers were provided by Nvidia.
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register "href_to_sync" = "1"
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register "hfront_porch" = "44"
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register "hsync_width" = "46"
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register "hback_porch" = "44"
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register "vref_to_sync" = "1"
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register "vfront_porch" = "3"
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register "vsync_width" = "10"
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register "vback_porch" = "36"
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register "vfront_porch" = "6"
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register "vsync_width" = "8"
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register "vback_porch" = "6"
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# we *know* the pixel clock for this system.
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register "pixel_clock" = "285"
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register "pixel_clock" = "71"
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end
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