broadwell: Update romstage main to follow baytrail format
This is a significant change that is hard to break up. The basic flow of the file comes from baytrail/romstage/romstage.c and was overlayed on top of the existing haswell romstage_main and fixed up where necessary. BUG=chrome-os-partner:28234 TEST=None Change-Id: I119c7033f4d2980f48e34ab413dfe4845491552b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/199361 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
chrome-internal-fetch
parent
a52d275e41
commit
0678c739af
1 changed files with 81 additions and 179 deletions
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@ -17,238 +17,140 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stddef.h>
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#include <stdint.h>
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#include <string.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <arch/cpu.h>
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#include <cpu/x86/bist.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/stack.h>
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#include <lib.h>
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#include <timestamp.h>
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#include <arch/io.h>
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#include <arch/cbfs.h>
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#include <arch/stages.h>
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#include <device/pci_def.h>
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#include <cpu/x86/lapic.h>
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#include <cbfs.h>
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#include <arch/early_variables.h>
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#include <console/console.h>
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#include <cbmem.h>
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#include <cpu/x86/mtrr.h>
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#include <elog.h>
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#include <ramstage_cache.h>
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#include <romstage_handoff.h>
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#include <reset.h>
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#include <timestamp.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#if CONFIG_EC_GOOGLE_CHROMEEC
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#include <ec/google/chromeec/ec.h>
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#endif
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#include "haswell.h"
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#include "northbridge/intel/haswell/haswell.h"
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#include "northbridge/intel/haswell/raminit.h"
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#include "southbridge/intel/lynxpoint/pch.h"
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#include "southbridge/intel/lynxpoint/me.h"
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#include <broadwell/me.h>
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#include <broadwell/pei_data.h>
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#include <broadwell/pm.h>
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#include <broadwell/reset.h>
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#include <broadwell/romstage.h>
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#include <broadwell/spi.h>
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static inline void reset_system(void)
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static inline void mark_ts(struct romstage_params *rp, uint64_t ts)
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{
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hard_reset();
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while (1) {
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hlt();
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}
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struct romstage_timestamps *rt = &rp->ts;
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rt->times[rt->count] = ts;
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rt->count++;
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}
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/* The cache-as-ram assembly file calls romstage_main() after setting up
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* cache-as-ram. romstage_main() will then call the mainboards's
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* mainboard_romstage_entry() function. That function then calls
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* romstage_common() below. The reason for the back and forth is to provide
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* common entry point from cache-as-ram while still allowing for code sharing.
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* Because we can't use global variables the stack is used for allocations --
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* thus the need to call back and forth. */
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void * asmlinkage romstage_main(unsigned long bist)
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/* Entry from cache-as-ram.inc. */
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void * asmlinkage romstage_main(unsigned long bist,
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uint32_t tsc_low, uint32_t tsc_hi)
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{
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int i;
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void *romstage_stack_after_car;
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const int num_guards = 4;
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const u32 stack_guard = 0xdeadbeef;
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u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE +
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CONFIG_DCACHE_RAM_SIZE -
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CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE);
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struct romstage_params rp = {
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.bist = bist,
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.pei_data = NULL,
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};
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printk(BIOS_DEBUG, "Setting up stack guards.\n");
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for (i = 0; i < num_guards; i++)
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stack_base[i] = stack_guard;
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post_code(0x30);
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mainboard_romstage_entry(bist);
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/* Save initial timestamp from bootblock. */
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mark_ts(&rp, (((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low);
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/* Check the stack. */
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for (i = 0; i < num_guards; i++) {
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if (stack_base[i] == stack_guard)
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continue;
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printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n");
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}
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/* Save romstage begin */
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mark_ts(&rp, timestamp_get());
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/* Get the stack to use after cache-as-ram is torn down. */
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romstage_stack_after_car = setup_romstage_stack_after_car();
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/* System Agent Early Initialization */
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systemagent_early_init();
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return romstage_stack_after_car;
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}
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/* PCH Early Initialization */
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pch_early_init();
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void romstage_common(const struct romstage_params *params)
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{
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int boot_mode;
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int wake_from_s3;
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struct romstage_handoff *handoff;
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#if CONFIG_COLLECT_TIMESTAMPS
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uint64_t start_romstage_time;
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uint64_t before_dram_time;
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uint64_t after_dram_time;
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uint64_t base_time =
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(uint64_t)pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) << 32 ||
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pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc);
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#endif
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#if CONFIG_COLLECT_TIMESTAMPS
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start_romstage_time = timestamp_get();
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#endif
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if (params->bist == 0)
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enable_lapic();
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wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config);
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#if CONFIG_EC_GOOGLE_CHROMEEC
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/* Ensure the EC is in the right mode for recovery */
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google_chromeec_early_init();
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#endif
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/* Halt if there was a built in self test failure */
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report_bist_failure(params->bist);
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/* Perform some early chipset initialization required
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* before RAM initialization can work
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*/
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haswell_early_initialization(HASWELL_MOBILE);
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printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n");
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if (wake_from_s3) {
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#if CONFIG_HAVE_ACPI_RESUME
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printk(BIOS_DEBUG, "Resume from S3 detected.\n");
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#else
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printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
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wake_from_s3 = 0;
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#endif
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}
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/* There are hard coded assumptions of 2 meaning s3 wake. Normalize
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* the users of the 2 literal here based off wake_from_s3. */
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boot_mode = wake_from_s3 ? 2 : 0;
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/* Prepare USB controller early in S3 resume */
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if (wake_from_s3)
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enable_usb_bar();
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post_code(0x3a);
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params->pei_data->boot_mode = boot_mode;
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#if CONFIG_COLLECT_TIMESTAMPS
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before_dram_time = timestamp_get();
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#endif
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/* Start console drivers */
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console_init();
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/* Print useful platform information */
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report_platform_info();
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if (params->copy_spd != NULL)
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params->copy_spd(params->pei_data);
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sdram_initialize(params->pei_data);
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/* Call into mainboard. */
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mainboard_romstage_entry(&rp);
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#if CONFIG_COLLECT_TIMESTAMPS
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after_dram_time = timestamp_get();
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return setup_stack_and_mttrs();
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}
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static inline void chromeos_init(int prev_sleep_state)
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{
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#if CONFIG_CHROMEOS
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/* Normalize the sleep state to what init_chromeos() wants for S3: 2 */
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init_chromeos(prev_sleep_state == SLEEP_STATE_S3 ? 2 : 0);
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#endif
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post_code(0x3b);
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}
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intel_early_me_status();
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/* Entry from the mainboard. */
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void romstage_common(struct romstage_params *params)
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{
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struct chipset_power_state *ps;
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struct romstage_handoff *handoff;
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quick_ram_check();
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post_code(0x3e);
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post_code(0x32);
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if (!wake_from_s3) {
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cbmem_initialize_empty();
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/* Save data returned from MRC on non-S3 resumes. */
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save_mrc_data(params->pei_data);
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} else if (cbmem_initialize()) {
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#if CONFIG_HAVE_ACPI_RESUME
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/* Failed S3 resume, reset to come up cleanly */
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reset_system();
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#endif
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}
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mark_ts(params, timestamp_get());
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/* Get power state */
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ps = fill_power_state();
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params->pei_data->boot_mode = ps->prev_sleep_state;
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#if CONFIG_ELOG_BOOT_COUNT
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if (ps->prev_sleep_state != SLEEP_STATE_S3)
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boot_count_increment();
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#endif
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/* Print ME state before MRC */
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intel_me_status();
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/* Initialize RAM */
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raminit(params->pei_data);
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mark_ts(params, timestamp_get());
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handoff = romstage_handoff_find_or_add();
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if (handoff != NULL)
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handoff->s3_resume = wake_from_s3;
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handoff->s3_resume = (ps->prev_sleep_state == SLEEP_STATE_S3);
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else
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printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
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post_code(0x3f);
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#if CONFIG_CHROMEOS
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init_chromeos(boot_mode);
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#endif
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#if CONFIG_COLLECT_TIMESTAMPS
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timestamp_init(base_time);
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timestamp_add(TS_START_ROMSTAGE, start_romstage_time );
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timestamp_add(TS_BEFORE_INITRAM, before_dram_time );
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timestamp_add(TS_AFTER_INITRAM, after_dram_time );
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chromeos_init(ps->prev_sleep_state);
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/* Save timestamp information. */
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timestamp_init(params->ts.times[0]);
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timestamp_add(TS_START_ROMSTAGE, params->ts.times[1]);
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timestamp_add(TS_BEFORE_INITRAM, params->ts.times[2]);
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timestamp_add(TS_AFTER_INITRAM, params->ts.times[3]);
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}
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void asmlinkage romstage_after_car(void)
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{
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timestamp_add_now(TS_END_ROMSTAGE);
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#endif
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}
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static inline void prepare_for_resume(struct romstage_handoff *handoff)
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{
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/* Only need to save memory when ramstage isn't relocatable. */
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#if !CONFIG_RELOCATABLE_RAMSTAGE
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#if CONFIG_HAVE_ACPI_RESUME
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/* Back up the OS-controlled memory where ramstage will be loaded. */
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if (handoff != NULL && handoff->s3_resume) {
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void *src = (void *)CONFIG_RAMBASE;
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void *dest = cbmem_find(CBMEM_ID_RESUME);
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if (dest != NULL)
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memcpy(dest, src, HIGH_MEMORY_SAVE);
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}
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#endif
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#endif
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}
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void romstage_after_car(void)
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{
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struct romstage_handoff *handoff;
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handoff = romstage_handoff_find_or_add();
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prepare_for_resume(handoff);
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vboot_verify_firmware(handoff);
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/* Run vboot verification if configured. */
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vboot_verify_firmware(romstage_handoff_find_or_add());
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/* Load the ramstage. */
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copy_and_run();
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}
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#if CONFIG_RELOCATABLE_RAMSTAGE
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#include <ramstage_cache.h>
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struct ramstage_cache *ramstage_cache_location(long *size)
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{
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/* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
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* The top of ram is defined to be the TSEG base address. */
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*size = RESERVED_SMM_SIZE;
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return (void *)(get_top_of_ram() + RESERVED_SMM_OFFSET);
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while (1);
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}
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void ramstage_cache_invalid(struct ramstage_cache *cache)
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{
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#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE
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/* Perform cold reset on invalid ramstage cache. */
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reset_system();
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#endif
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}
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#endif
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#if CONFIG_CHROMEOS
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int vboot_get_sw_write_protect(void)
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