broadwell: Add reference code data interface
Add the header file used to communicate information to the intel reference code binaries. This is shared directly with the PEI wrapper in the binary. A broadwell specific function is defined to fill out platform specific information and a function prototype is provided for the mainboard to implement. BUG=chrome-os-partner:28234 TEST=None Change-Id: Ib3254cbd0c1a890ffb716cab551f68b6201812d2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198743 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
chrome-internal-fetch
parent
69d5b7c834
commit
9059b8e230
3 changed files with 274 additions and 0 deletions
177
src/soc/intel/broadwell/broadwell/pei_data.h
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177
src/soc/intel/broadwell/broadwell/pei_data.h
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/*
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* Broadwell UEFI PEI wrapper
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*
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* Copyright (C) 2014 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Google Inc. nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef PEI_DATA_H
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#define PEI_DATA_H
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#include <types.h>
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#define PEI_VERSION 20
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#define ABI_X86 __attribute__((regparm(0)))
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typedef void ABI_X86 (*tx_byte_func)(unsigned char byte);
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enum board_type {
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BOARD_TYPE_CRB_MOBILE = 0, /* CRB Mobile */
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BOARD_TYPE_CRB_DESKTOP, /* CRB Desktop */
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BOARD_TYPE_USER1, /* SV mobile */
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BOARD_TYPE_USER2, /* SV desktop */
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BOARD_TYPE_USER3, /* SV server */
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BOARD_TYPE_ULT, /* ULT */
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BOARD_TYPE_CRB_EMBDEDDED, /* CRB Embedded */
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BOARD_TYPE_UNKNOWN,
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};
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#define MAX_USB2_PORTS 14
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#define MAX_USB3_PORTS 6
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#define USB_OC_PIN_SKIP 8
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enum usb2_port_location {
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USB_PORT_BACK_PANEL = 0,
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USB_PORT_FRONT_PANEL,
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USB_PORT_DOCK,
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USB_PORT_MINI_PCIE,
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USB_PORT_FLEX,
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USB_PORT_INTERNAL,
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USB_PORT_SKIP,
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USB_PORT_NGFF_DEVICE_DOWN,
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};
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struct usb2_port_setting {
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/*
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* Usb Port Length:
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* [16:4] = length in inches in octal format
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* [3:0] = decimal point
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*/
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uint16_t length;
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uint8_t enable;
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uint8_t oc_pin;
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uint8_t location;
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} __attribute__((packed));
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struct usb3_port_setting {
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uint8_t enable;
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uint8_t oc_pin;
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/*
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* Set to 0 if trace length is > 5 inches
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* Set to 1 if trace length is <= 5 inches
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*/
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uint8_t fixed_eq;
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} __attribute__((packed));
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struct pei_data
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{
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uint32_t pei_version;
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enum board_type board_type;
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int boot_mode;
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int ec_present;
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int usbdebug;
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/* Base addresses */
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uint32_t pciexbar;
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uint16_t smbusbar;
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uint32_t xhcibar;
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uint32_t ehcibar;
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uint32_t gttbar;
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uint32_t rcba;
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uint32_t pmbase;
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uint32_t gpiobase;
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uint32_t temp_mmio_base;
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uint32_t tseg_size;
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/*
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* 0 = leave channel enabled
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* 1 = disable dimm 0 on channel
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* 2 = disable dimm 1 on channel
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* 3 = disable dimm 0+1 on channel
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*/
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int dimm_channel0_disabled;
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int dimm_channel1_disabled;
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/* Set to 0 for memory down */
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uint8_t spd_addresses[4];
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/* Enable 2x Refresh Mode */
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int ddr_refresh_2x;
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/* DQ pins are interleaved on board */
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int dq_pins_interleaved;
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/* Limit DDR3 frequency */
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int max_ddr3_freq;
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/* USB port configuration */
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struct usb2_port_setting usb2_ports[MAX_USB2_PORTS];
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struct usb3_port_setting usb3_ports[MAX_USB3_PORTS];
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/* Console output function */
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tx_byte_func tx_byte;
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/*
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* DIMM SPD data for memory down configurations
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* [CHANNEL][SLOT][SPD]
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*/
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uint8_t spd_data[2][2][512];
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/*
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* LPDDR3 DQ byte map
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* [CHANNEL][ITERATION][2]
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*
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* Maps which PI clocks are used by what LPDDR DQ Bytes (from CPU side)
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* DQByteMap[0] - ClkDQByteMap:
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* - If clock is per rank, program to [0xFF, 0xFF]
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* - If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]
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* - If clock is shared by 2 ranks but does not go to all bytes,
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* Entry[i] defines which DQ bytes Group i services
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* DQByteMap[1] - CmdNDQByteMap: [0] is CmdN/CAA and [1] is CmdN/CAB
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* DQByteMap[2] - CmdSDQByteMap: [0] is CmdS/CAA and [1] is CmdS/CAB
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* DQByteMap[3] - CkeDQByteMap : [0] is CKE /CAA and [1] is CKE /CAB
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* For DDR, DQByteMap[3:1] = [0xFF, 0]
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* DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0]
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* since we have 1 CTL / rank
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* DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0]
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* since we have 1 CA Vref
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*/
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uint8_t dq_map[2][6][2];
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/*
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* LPDDR3 Map from CPU DQS pins to SDRAM DQS pins
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* [CHANNEL][MAX_BYTES]
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*/
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uint8_t dqs_map[2][8];
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/* Data read from flash and passed into MRC */
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const void *saved_data;
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int saved_data_size;
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/* Data from MRC that should be saved to flash */
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void *data_to_save;
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int data_to_save_size;
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} __attribute__((packed));
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typedef struct pei_data PEI_DATA;
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#endif
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49
src/soc/intel/broadwell/broadwell/pei_wrapper.h
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49
src/soc/intel/broadwell/broadwell/pei_wrapper.h
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef _BROADWELL_PEI_WRAPPER_H_
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#define _BROADWELL_PEI_WRAPPER_H_
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#include <broadwell/pei_data.h>
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typedef int ABI_X86 (*pei_wrapper_entry_t)(struct pei_data *pei_data);
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static inline void pei_data_usb2_port(struct pei_data *pei_data, int port,
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uint16_t length, uint8_t enable,
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uint8_t oc_pin, uint8_t location)
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{
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pei_data->usb2_ports[port].length = length;
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pei_data->usb2_ports[port].enable = enable;
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pei_data->usb2_ports[port].oc_pin = oc_pin;
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pei_data->usb2_ports[port].location = location;
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}
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static inline void pei_data_usb3_port(struct pei_data *pei_data, int port,
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uint8_t enable, uint8_t oc_pin,
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uint8_t fixed_eq)
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{
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pei_data->usb3_ports[port].enable = enable;
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pei_data->usb3_ports[port].oc_pin = oc_pin;
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pei_data->usb3_ports[port].fixed_eq = fixed_eq;
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}
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void broadwell_fill_pei_data(struct pei_data *pei_data);
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void mainboard_fill_pei_data(struct pei_data *pei_data);
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#endif
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48
src/soc/intel/broadwell/pei_data.c
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48
src/soc/intel/broadwell/pei_data.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <broadwell/iomap.h>
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#include <broadwell/pei_data.h>
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#include <broadwell/pei_wrapper.h>
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#include <broadwell/smm.h>
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static void ABI_X86 send_to_console(unsigned char b)
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{
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console_tx_byte(b);
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}
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void broadwell_fill_pei_data(struct pei_data *pei_data)
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{
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pei_data->pei_version = PEI_VERSION;
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pei_data->board_type = BOARD_TYPE_ULT;
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pei_data->usbdebug = CONFIG_USBDEBUG;
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pei_data->pciexbar = MCFG_BASE_ADDRESS;
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pei_data->smbusbar = SMBUS_BASE_ADDRESS;
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pei_data->ehcibar = EARLY_EHCI_BAR;
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pei_data->xhcibar = EARLY_XHCI_BAR;
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pei_data->gttbar = EARLY_GTT_BAR;
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pei_data->pmbase = ACPI_BASE_ADDRESS;
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pei_data->gpiobase = GPIO_BASE_ADDRESS;
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pei_data->tseg_size = smm_region_size();
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pei_data->temp_mmio_base = EARLY_TEMP_MMIO;
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pei_data->tx_byte = &send_to_console;
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}
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