broadwell: Clean up SMM code
- Use device macros from pci_devs.h - Use base addresses from iobase.h - Clean up some code and comment formatting - Remove the SMI that would route USB to XHCI since this is now done by default at boot time. BUG=chrome-os-partner:28234 TEST=None Change-Id: If448b28f2c41c4533c449da8cf63f261c38b5939 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/199391 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
chrome-internal-fetch
parent
ddc4c116b4
commit
8295e56c9b
3 changed files with 40 additions and 67 deletions
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@ -26,16 +26,19 @@
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#include <cpu/x86/cache.h>
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#include <cpu/x86/smm.h>
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#include <string.h>
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#include "pch.h"
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#include <broadwell/iomap.h>
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#include <broadwell/pch.h>
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#include <broadwell/pm.h>
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#include <broadwell/smm.h>
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void southbridge_smm_clear_state(void)
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{
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u32 smi_en;
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printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
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printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", get_pmbase());
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printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", ACPI_BASE_ADDRESS);
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smi_en = inl(get_pmbase() + SMI_EN);
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smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN);
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if (smi_en & APMC_EN) {
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printk(BIOS_INFO, "SMI# handler already enabled?\n");
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return;
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@ -26,16 +26,21 @@
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#include <cpu/x86/cache.h>
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#include <device/pci_def.h>
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#include <cpu/x86/smm.h>
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#include <spi-generic.h>
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#include <elog.h>
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#include <pc80/mc146818rtc.h>
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#include "pch.h"
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#include "nvs.h"
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#include <broadwell/lpc.h>
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#include <broadwell/nvs.h>
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#include <broadwell/pci_devs.h>
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#include <broadwell/pm.h>
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#include <broadwell/rcba.h>
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#include <broadwell/smm.h>
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#include <broadwell/xhci.h>
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static u8 smm_initialized = 0;
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/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
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/*
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* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
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* by coreboot.
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*/
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static global_nvs_t *gnvs;
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@ -111,9 +116,8 @@ static void southbridge_smi_sleep(void)
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u32 reg32;
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u8 slp_typ;
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u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
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u16 pmbase = get_pmbase();
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// save and recover RTC port values
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/* save and recover RTC port values */
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u8 tmp70, tmp72;
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tmp70 = inb(0x70);
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tmp72 = inb(0x72);
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@ -125,7 +129,7 @@ static void southbridge_smi_sleep(void)
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disable_smi(SLP_SMI_EN);
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/* Figure out SLP_TYP */
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reg32 = inl(pmbase + PM1_CNT);
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reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT);
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printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
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slp_typ = (reg32 >> 10) & 7;
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@ -133,11 +137,7 @@ static void southbridge_smi_sleep(void)
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mainboard_smi_sleep(slp_typ-2);
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/* USB sleep preparations */
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#if !CONFIG_FINALIZE_USB_ROUTE_XHCI
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usb_ehci_sleep_prepare(PCH_EHCI1_DEV, slp_typ);
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usb_ehci_sleep_prepare(PCH_EHCI2_DEV, slp_typ);
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#endif
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usb_xhci_sleep_prepare(PCH_XHCI_DEV, slp_typ);
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usb_xhci_sleep_prepare(PCH_DEV_XHCI, slp_typ);
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#if CONFIG_ELOG_GSMI
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/* Log S3, S4, and S5 entry */
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@ -173,13 +173,12 @@ static void southbridge_smi_sleep(void)
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/* Always set the flag in case CMOS was changed on runtime. For
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* "KEEP", switch to "OFF" - KEEP is software emulated
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*/
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reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
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if (s5pwr == MAINBOARD_POWER_ON) {
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reg8 = pci_read_config8(PCH_DEV_LPC, GEN_PMCON_3);
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if (s5pwr == MAINBOARD_POWER_ON)
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reg8 &= ~1;
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} else {
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else
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reg8 |= 1;
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}
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pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
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pci_write_config8(PCH_DEV_LPC, GEN_PMCON_3, reg8);
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/* also iterates over all bridges on bus 0 */
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busmaster_disable_on_bus(0);
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@ -189,7 +188,8 @@ static void southbridge_smi_sleep(void)
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break;
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}
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/* Write back to the SLP register to cause the originally intended
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/*
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* Write back to the SLP register to cause the originally intended
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* event again. We need to set BIT13 (SLP_EN) though to make the
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* sleep happen.
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*/
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@ -199,11 +199,12 @@ static void southbridge_smi_sleep(void)
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if (slp_typ > 1)
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hlt();
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/* In most sleep states, the code flow of this function ends at
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/*
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* In most sleep states, the code flow of this function ends at
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* the line above. However, if we entered sleep state S1 and wake
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* up again, we will continue to execute code in this function.
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*/
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reg32 = inl(pmbase + PM1_CNT);
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reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT);
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if (reg32 & SCI_EN) {
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/* The OS is not an ACPI OS, so we set the state to S0 */
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disable_pm1_control(SLP_EN | SLP_TYP);
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@ -295,17 +296,9 @@ static void southbridge_smi_apmc(void)
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reg8 = inb(APM_CNT);
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switch (reg8) {
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case APM_CNT_CST_CONTROL:
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/* Calling this function seems to cause
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* some kind of race condition in Linux
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* and causes a kernel oops
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*/
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printk(BIOS_DEBUG, "C-state control\n");
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break;
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case APM_CNT_PST_CONTROL:
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/* Calling this function seems to cause
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* some kind of race condition in Linux
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* and causes a kernel oops
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*/
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printk(BIOS_DEBUG, "P-state control\n");
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break;
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case APM_CNT_ACPI_DISABLE:
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@ -333,9 +326,6 @@ static void southbridge_smi_apmc(void)
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printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
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}
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break;
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case 0xca:
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usb_xhci_route_all();
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break;
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#if CONFIG_ELOG_GSMI
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case ELOG_GSMI_APM_CNT:
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southbridge_smi_gsmi();
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@ -354,7 +344,7 @@ static void southbridge_smi_pm1(void)
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* on a power button event.
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*/
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if (pm1_sts & PWRBTN_STS) {
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// power button pressed
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/* power button pressed */
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#if CONFIG_ELOG_GSMI
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elog_add_event(ELOG_TYPE_POWER_BUTTON);
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#endif
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@ -378,9 +368,7 @@ static void southbridge_smi_gpi(void)
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static void southbridge_smi_mc(void)
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{
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u32 reg32;
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reg32 = inl(get_pmbase() + SMI_EN);
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u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN);
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/* Are microcontroller SMIs enabled? */
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if ((reg32 & MCSMI_EN) == 0)
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@ -389,8 +377,6 @@ static void southbridge_smi_mc(void)
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printk(BIOS_DEBUG, "Microcontroller SMI.\n");
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}
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static void southbridge_smi_tco(void)
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{
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u32 tco_sts = clear_tco_status();
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@ -400,23 +386,21 @@ static void southbridge_smi_tco(void)
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return;
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if (tco_sts & (1 << 8)) { // BIOSWR
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u8 bios_cntl;
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bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
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u8 bios_cntl = pci_read_config16(PCH_DEV_LPC, BIOS_CNTL);
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if (bios_cntl & 1) {
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/* BWE is RW, so the SMI was caused by a
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/*
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* BWE is RW, so the SMI was caused by a
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* write to BWE, not by a write to the BIOS
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*/
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/* This is the place where we notice someone
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*
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* This is the place where we notice someone
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* is trying to tinker with the BIOS. We are
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* trying to be nice and just ignore it. A more
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* resolute answer would be to power down the
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* box.
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*/
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printk(BIOS_DEBUG, "Switching back to RO\n");
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc,
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pci_write_config32(PCH_DEV_LPC, BIOS_CNTL,
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(bios_cntl & ~1));
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} /* No else for now? */
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} else if (tco_sts & (1 << 3)) { /* TIMEOUT */
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@ -427,9 +411,7 @@ static void southbridge_smi_tco(void)
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static void southbridge_smi_periodic(void)
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{
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u32 reg32;
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reg32 = inl(get_pmbase() + SMI_EN);
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u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN);
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/* Are periodic SMIs enabled? */
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if ((reg32 & PERIODIC_EN) == 0)
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@ -29,12 +29,9 @@
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <console/console.h>
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#include <northbridge/intel/haswell/haswell.h>
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#include <southbridge/intel/lynxpoint/pch.h>
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#include "haswell.h"
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#include <broadwell/cpu.h>
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#include <broadwell/msr.h>
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#include <broadwell/pci_devs.h>
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#include <broadwell/smm.h>
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#include <broadwell/systemagent.h>
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@ -326,11 +323,6 @@ static void setup_ied_area(struct smm_relocation_params *params)
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/* Zero out 32KiB at IEDBASE + 1MiB */
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memset(ied_base + (1 << 20), 0, (32 << 10));
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/* According to the BWG MP init section 2MiB of memory at IEDBASE +
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* 2MiB should be zeroed as well. However, I suspect what is inteneded
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* is to clear the memory covered by EMRR. TODO(adurbin): figure out if * this is really required. */
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//memset(ied_base + (2 << 20), 0, (2 << 20));
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}
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static int install_permanent_handler(int num_cpus,
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@ -359,14 +351,12 @@ static int install_permanent_handler(int num_cpus,
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static int cpu_smm_setup(void)
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{
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device_t dev;
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device_t dev = SA_DEV_ROOT;
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int num_cpus;
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msr_t msr;
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printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
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dev = dev_find_slot(0, PCI_DEVFN(0, 0));
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fill_in_relocation_params(dev, &smm_reloc_params);
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setup_ied_area(&smm_reloc_params);
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@ -445,7 +435,5 @@ void smm_lock(void)
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* make the SMM registers writable again.
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*/
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printk(BIOS_DEBUG, "Locking SMM.\n");
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pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
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D_LCK | G_SMRAME | C_BASE_SEG);
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pci_write_config8(SA_DEV_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
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}
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