broadwell: romstage: Separate stack helper functions
Move the stack related helper functions to a separate file at broadwell/romstage/stack.c. BUG=chrome-os-partner:28234 TEST=None Change-Id: I9a89899c505e5a99615dd0e4b46a3487e04089f2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/199189 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
chrome-internal-fetch
parent
8a457b8261
commit
c220383c90
2 changed files with 124 additions and 101 deletions
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@ -63,107 +63,6 @@ static inline void reset_system(void)
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* Because we can't use global variables the stack is used for allocations --
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* thus the need to call back and forth. */
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static inline u32 *stack_push(u32 *stack, u32 value)
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{
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stack = &stack[-1];
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*stack = value;
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return stack;
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}
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/* Romstage needs quite a bit of stack for decompressing images since the lzma
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* lib keeps its state on the stack during romstage. */
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#define ROMSTAGE_RAM_STACK_SIZE 0x5000
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static unsigned long choose_top_of_stack(void)
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{
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unsigned long stack_top;
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#if CONFIG_DYNAMIC_CBMEM
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/* cbmem_add() does a find() before add(). */
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stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK,
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ROMSTAGE_RAM_STACK_SIZE);
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stack_top += ROMSTAGE_RAM_STACK_SIZE;
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#else
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stack_top = ROMSTAGE_STACK;
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#endif
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return stack_top;
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}
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/* setup_romstage_stack_after_car() determines the stack to use after
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* cache-as-ram is torn down as well as the MTRR settings to use. */
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static void *setup_romstage_stack_after_car(void)
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{
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unsigned long top_of_stack;
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int num_mtrrs;
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u32 *slot;
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u32 mtrr_mask_upper;
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u32 top_of_ram;
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/* Top of stack needs to be aligned to a 4-byte boundary. */
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top_of_stack = choose_top_of_stack() & ~3;
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slot = (void *)top_of_stack;
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num_mtrrs = 0;
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/* The upper bits of the MTRR mask need to set according to the number
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* of physical address bits. */
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mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1;
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/* The order for each MTTR is value then base with upper 32-bits of
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* each value coming before the lower 32-bits. The reasoning for
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* this ordering is to create a stack layout like the following:
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* +0: Number of MTRRs
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* +4: MTTR base 0 31:0
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* +8: MTTR base 0 63:32
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* +12: MTTR mask 0 31:0
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* +16: MTTR mask 0 63:32
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* +20: MTTR base 1 31:0
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* +24: MTTR base 1 63:32
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* +28: MTTR mask 1 31:0
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* +32: MTTR mask 1 63:32
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*/
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/* Cache the ROM as WP just below 4GiB. */
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slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
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slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRRphysMaskValid);
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slot = stack_push(slot, 0); /* upper base */
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slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
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num_mtrrs++;
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/* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */
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slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
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slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid);
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slot = stack_push(slot, 0); /* upper base */
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slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK);
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num_mtrrs++;
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top_of_ram = get_top_of_ram();
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/* Cache 8MiB below the top of ram. On haswell systems the top of
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* ram under 4GiB is the start of the TSEG region. It is required to
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* be 8MiB aligned. Set this area as cacheable so it can be used later
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* for ramstage before setting up the entire RAM as cacheable. */
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slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
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slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid);
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slot = stack_push(slot, 0); /* upper base */
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slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK);
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num_mtrrs++;
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/* Cache 8MiB at the top of ram. Top of ram on haswell systems
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* is where the TSEG region resides. However, it is not restricted
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* to SMM mode until SMM has been relocated. By setting the region
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* to cacheable it provides faster access when relocating the SMM
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* handler as well as using the TSEG region for other purposes. */
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slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
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slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid);
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slot = stack_push(slot, 0); /* upper base */
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slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK);
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num_mtrrs++;
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/* Save the number of MTTRs to setup. Return the stack location
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* pointing to the number of MTRRs. */
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slot = stack_push(slot, num_mtrrs);
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return slot;
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}
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void * asmlinkage romstage_main(unsigned long bist)
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{
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int i;
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124
src/soc/intel/broadwell/romstage/stack.c
Normal file
124
src/soc/intel/broadwell/romstage/stack.c
Normal file
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@ -0,0 +1,124 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stddef.h>
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#include <stdint.h>
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#include <arch/cpu.h>
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#include <arch/early_variables.h>
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#include <console/console.h>
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#include <cbmem.h>
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#include <cpu/x86/mtrr.h>
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#include <broadwell/romstage.h>
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static inline uint32_t *stack_push(u32 *stack, u32 value)
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{
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stack = &stack[-1];
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*stack = value;
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return stack;
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}
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/* Romstage needs quite a bit of stack for decompressing images since the lzma
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* lib keeps its state on the stack during romstage. */
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static unsigned long choose_top_of_stack(void)
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{
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unsigned long stack_top;
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const unsigned long romstage_ram_stack_size = 0x5000;
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/* cbmem_add() does a find() before add(). */
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stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK,
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romstage_ram_stack_size);
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stack_top += romstage_ram_stack_size;
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return stack_top;
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}
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/* setup_stack_and_mttrs() determines the stack to use after
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* cache-as-ram is torn down as well as the MTRR settings to use. */
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void *setup_stack_and_mttrs(void)
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{
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unsigned long top_of_stack;
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int num_mtrrs;
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uint32_t *slot;
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uint32_t mtrr_mask_upper;
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uint32_t top_of_ram;
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/* Top of stack needs to be aligned to a 4-byte boundary. */
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top_of_stack = choose_top_of_stack() & ~3;
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slot = (void *)top_of_stack;
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num_mtrrs = 0;
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/* The upper bits of the MTRR mask need to set according to the number
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* of physical address bits. */
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mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1;
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/* The order for each MTTR is value then base with upper 32-bits of
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* each value coming before the lower 32-bits. The reasoning for
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* this ordering is to create a stack layout like the following:
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* +0: Number of MTRRs
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* +4: MTTR base 0 31:0
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* +8: MTTR base 0 63:32
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* +12: MTTR mask 0 31:0
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* +16: MTTR mask 0 63:32
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* +20: MTTR base 1 31:0
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* +24: MTTR base 1 63:32
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* +28: MTTR mask 1 31:0
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* +32: MTTR mask 1 63:32
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*/
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/* Cache the ROM as WP just below 4GiB. */
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slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
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slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRRphysMaskValid);
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slot = stack_push(slot, 0); /* upper base */
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slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
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num_mtrrs++;
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/* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */
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slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
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slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid);
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slot = stack_push(slot, 0); /* upper base */
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slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK);
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num_mtrrs++;
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top_of_ram = (uint32_t)cbmem_top();
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/* Cache 8MiB below the top of ram. The top of ram under 4GiB is the
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* start of the TSEG region. It is required to be 8MiB aligned. Set
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* this area as cacheable so it can be used later for ramstage before
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* setting up the entire RAM as cacheable. */
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slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
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slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid);
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slot = stack_push(slot, 0); /* upper base */
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slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK);
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num_mtrrs++;
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/* Cache 8MiB at the top of ram. Top of ram is where the TSEG
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* region resides. However, it is not restricted to SMM mode until
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* SMM has been relocated. By setting the region to cacheable it
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* provides faster access when relocating the SMM handler as well
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* as using the TSEG region for other purposes. */
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slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
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slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid);
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slot = stack_push(slot, 0); /* upper base */
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slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK);
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num_mtrrs++;
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/* Save the number of MTTRs to setup. Return the stack location
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* pointing to the number of MTRRs. */
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slot = stack_push(slot, num_mtrrs);
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return slot;
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}
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