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tegra124: fix clear_fifo_status() in SPI driver

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The bits in the mask are wrong now that we're using the #defines
with all the bits shifted into place already (before it was just
a number that needed shifting).

BUG=none
BRANCH=none
TEST=built and booted on nyan, which isn't saying much since we
aren't having FIFO issues. Still, this is a pretty obvious fix.

Change-Id: Iddd52be8bf0f801afeb731a06befb5c9612ec8b1
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173738
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
This commit is contained in:
David Hendricks 2013-10-18 17:10:32 -07:00 • committed by chrome-internal-fetch
commit f415d2c0aa
1 changed files with 5 additions and 5 deletions
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10
src/soc/nvidia/tegra124/spi.c
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@ -300,11 +300,11 @@ static void dump_fifo_status(struct tegra_spi_channel *spi)
static void clear_fifo_status(struct tegra_spi_channel *spi)
{
clrbits_le32(&spi->regs->fifo_status,
(SPI_FIFO_STATUS_ERR |
SPI_FIFO_STATUS_TX_FIFO_OVF |
SPI_FIFO_STATUS_TX_FIFO_UNR |
SPI_FIFO_STATUS_RX_FIFO_OVF |
SPI_FIFO_STATUS_RX_FIFO_UNR) << 4);
SPI_FIFO_STATUS_ERR |
SPI_FIFO_STATUS_TX_FIFO_OVF |
SPI_FIFO_STATUS_TX_FIFO_UNR |
SPI_FIFO_STATUS_RX_FIFO_OVF |
SPI_FIFO_STATUS_RX_FIFO_UNR);
}
static void dump_spi_regs(struct tegra_spi_channel *spi)