tegra124: norrin: the first step to clean up display code
Remove many no longer needed code and files. More clean up will be followed. BUG=none BRANCH=none TEST=build and boot up graphic Change-Id: I72471be01e7c9b5244aff12b45f887dd35dfe58e Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-on: https://chromium-review.googlesource.com/180135 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org>
This commit is contained in:
Jimmy Zhang
chrome-internal-fetch
parent
03b5e88a66
commit
9d0c12dfef
5 changed files with 192 additions and 54604 deletions
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@ -37,9 +37,6 @@
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#include "chip.h"
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#include "sor.h"
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#include <soc/display.h>
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#include <soc/ardisplay.h>
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#include <soc/arsor.h>
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#include <soc/ardpaux.h>
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//#include <soc/nvidia/tegra/displayport.h>
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extern int dump;
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@ -77,269 +74,38 @@ void init_dca_regs(void)
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}
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#endif
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DCA_WRITE(DC_DISP_DISP_CLOCK_CONTROL_0, 0x00000006); //0x542410b8
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DCA_WRITE(DC_CMD_INT_STATUS_0, 0xffffffff); //0x542400dc
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DCA_WRITE(DC_CMD_INT_MASK_0, 0x00000000); //0x542400e0
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DCA_WRITE(DC_CMD_INT_ENABLE_0, 0x00800701); //0x542400e4
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DCA_WRITE(DC_CMD_INT_POLARITY_0, 0x00c00706); //0x542400ec
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DCA_WRITE(DC_DISP_DISP_SIGNAL_OPTIONS0_0, 0x00000000); //0x54241000
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DCA_WRITE(DC_DISP_DISP_SIGNAL_OPTIONS1_0, 0x00000000); //0x54241004
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DCA_WRITE(DC_DISP_DISP_WIN_OPTIONS_0, 0x00000000); //0x54241008
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DCA_WRITE(DC_DISP_MEM_HIGH_PRIORITY_0, 0x00000000); //0x5424100c
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DCA_WRITE(DC_DISP_MEM_HIGH_PRIORITY_TIMER_0, 0x00000000); //0x54241010
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DCA_WRITE(DC_DISP_DISP_TIMING_OPTIONS_0, 0x00000000); //0x54241014
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DCA_WRITE(DC_DISP_REF_TO_SYNC_0, 0x00000000); //0x54241018
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DCA_WRITE(DC_DISP_SYNC_WIDTH_0, 0x00000000); //0x5424101c
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DCA_WRITE(DC_DISP_BACK_PORCH_0, 0x00000000); //0x54241020
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DCA_WRITE(DC_DISP_DISP_ACTIVE_0, 0x00030003); //0x54241024
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DCA_WRITE(DC_DISP_FRONT_PORCH_0, 0x00000000); //0x54241028
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DCA_WRITE(DC_DISP_H_PULSE0_CONTROL_0, 0x00000000); //0x5424102c
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DCA_WRITE(DC_DISP_H_PULSE0_POSITION_A_0, 0x00000000); //0x54241030
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DCA_WRITE(DC_DISP_H_PULSE0_POSITION_B_0, 0x00000000); //0x54241034
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DCA_WRITE(DC_DISP_H_PULSE0_POSITION_C_0, 0x00000000); //0x54241038
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DCA_WRITE(DC_DISP_H_PULSE0_POSITION_D_0, 0x00000000); //0x5424103c
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DCA_WRITE(DC_DISP_H_PULSE1_CONTROL_0, 0x00000000); //0x54241040
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DCA_WRITE(DC_DISP_H_PULSE1_POSITION_A_0, 0x00000000); //0x54241044
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DCA_WRITE(DC_DISP_H_PULSE1_POSITION_B_0, 0x00000000); //0x54241048
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DCA_WRITE(DC_DISP_H_PULSE1_POSITION_C_0, 0x00000000); //0x5424104c
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DCA_WRITE(DC_DISP_H_PULSE1_POSITION_D_0, 0x00000000); //0x54241050
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DCA_WRITE(DC_DISP_H_PULSE2_CONTROL_0, 0x00000000); //0x54241054
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DCA_WRITE(DC_DISP_H_PULSE2_POSITION_A_0, 0x00000000); //0x54241058
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DCA_WRITE(DC_DISP_H_PULSE2_POSITION_B_0, 0x00000000); //0x5424105c
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DCA_WRITE(DC_DISP_H_PULSE2_POSITION_C_0, 0x00000000); //0x54241060
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DCA_WRITE(DC_DISP_H_PULSE2_POSITION_D_0, 0x00000000); //0x54241064
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DCA_WRITE(DC_DISP_V_PULSE0_CONTROL_0, 0x00000000); //0x54241068
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DCA_WRITE(DC_DISP_V_PULSE0_POSITION_A_0, 0x00000000); //0x5424106c
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DCA_WRITE(DC_DISP_V_PULSE0_POSITION_B_0, 0x00000000); //0x54241070
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DCA_WRITE(DC_DISP_V_PULSE0_POSITION_C_0, 0x00000000); //0x54241074
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DCA_WRITE(DC_DISP_V_PULSE1_CONTROL_0, 0x00000000); //0x54241078
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DCA_WRITE(DC_DISP_V_PULSE1_POSITION_A_0, 0x00000000); //0x5424107c
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DCA_WRITE(DC_DISP_V_PULSE1_POSITION_B_0, 0x00000000); //0x54241080
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DCA_WRITE(DC_DISP_V_PULSE1_POSITION_C_0, 0x00000000); //0x54241084
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DCA_WRITE(DC_DISP_V_PULSE2_CONTROL_0, 0x00000000); //0x54241088
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DCA_WRITE(DC_DISP_V_PULSE2_POSITION_A_0, 0x00000000); //0x5424108c
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DCA_WRITE(DC_DISP_V_PULSE3_CONTROL_0, 0x00000000); //0x54241090
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DCA_WRITE(DC_DISP_V_PULSE3_POSITION_A_0, 0x00000000); //0x54241094
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DCA_WRITE(DC_DISP_M0_CONTROL_0, 0x00000000); //0x54241098
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DCA_WRITE(DC_DISP_M1_CONTROL_0, 0x00000000); //0x5424109c
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DCA_WRITE(DC_DISP_DI_CONTROL_0, 0x00000000); //0x542410a0
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DCA_WRITE(DC_DISP_PP_CONTROL_0, 0x00000000); //0x542410a4
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DCA_WRITE(DC_DISP_PP_SELECT_A_0, 0x00000000); //0x542410a8
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DCA_WRITE(DC_DISP_PP_SELECT_B_0, 0x00000000); //0x542410ac
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DCA_WRITE(DC_DISP_PP_SELECT_C_0, 0x00000000); //0x542410b0
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DCA_WRITE(DC_DISP_PP_SELECT_D_0, 0x00000000); //0x542410b4
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DCA_WRITE(DC_DISP_DISP_INTERFACE_CONTROL_0, 0x00000000); //0x542410bc
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DCA_WRITE(DC_DISP_DISP_COLOR_CONTROL_0, 0x00000000); //0x542410c0
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DCA_WRITE(DC_DISP_SHIFT_CLOCK_OPTIONS_0, 0x00000000); //0x542410c4
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DCA_WRITE(DC_DISP_DATA_ENABLE_OPTIONS_0, 0x00000000); //0x542410c8
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DCA_WRITE(DC_DISP_SERIAL_INTERFACE_OPTIONS_0, 0x00000000); //0x542410cc
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DCA_WRITE(DC_DISP_LCD_SPI_OPTIONS_0, 0x00000000); //0x542410d0
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DCA_WRITE(DC_DISP_COLOR_KEY0_LOWER_0, 0x00000000); //0x542410d8
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DCA_WRITE(DC_DISP_COLOR_KEY0_UPPER_0, 0x00000000); //0x542410dc
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DCA_WRITE(DC_DISP_COLOR_KEY1_LOWER_0, 0x00000000); //0x542410e0
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DCA_WRITE(DC_DISP_COLOR_KEY1_UPPER_0, 0x00000000); //0x542410e4
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DCA_WRITE(DC_DISP_CURSOR_FOREGROUND_0, 0x00000000); //0x542410f0
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DCA_WRITE(DC_DISP_CURSOR_BACKGROUND_0, 0x00000000); //0x542410f4
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DCA_WRITE(DC_DISP_CURSOR_START_ADDR_0, 0x00200000); //0x542410f8
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DCA_WRITE(DC_DISP_CURSOR_START_ADDR_NS_0, 0x00000000); //0x542410fc
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DCA_WRITE(DC_DISP_CURSOR_POSITION_0, 0x00000000); //0x54241100
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DCA_WRITE(DC_DISP_CURSOR_POSITION_NS_0, 0x00000000); //0x54241104
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DCA_WRITE(DC_DISP_INIT_SEQ_CONTROL_0, 0x00000000); //0x54241108
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DCA_WRITE(DC_DISP_SPI_INIT_SEQ_DATA_A_0, 0x00000000); //0x5424110c
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DCA_WRITE(DC_DISP_SPI_INIT_SEQ_DATA_B_0, 0x00000000); //0x54241110
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DCA_WRITE(DC_DISP_SPI_INIT_SEQ_DATA_C_0, 0x00000000); //0x54241114
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DCA_WRITE(DC_DISP_SPI_INIT_SEQ_DATA_D_0, 0x00000000); //0x54241118
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DCA_WRITE(DC_DISP_DC_MCCIF_FIFOCTRL_0, 0x00000000); //0x54241200
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DCA_WRITE(DC_DISP_MCCIF_DISPLAY0A_HYST_0, 0xcf401f1f); //0x54241204
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DCA_WRITE(DC_DISP_MCCIF_DISPLAY0B_HYST_0, 0xcf401f1f); //0x54241208
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DCA_WRITE(DC_DISP_MCCIF_DISPLAY0C_HYST_0, 0xcf401f1f); //0x5424120c
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DCA_WRITE(DC_DISP_DISP_MISC_CONTROL_0, 0x00000002); //0x54241304
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DCA_WRITE(DC_DISP_SD_CONTROL_0, 0x00004000); //0x54241308
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DCA_WRITE(DC_DISP_SD_CSC_COEFF_0, 0x00000000); //0x5424130c
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DCA_WRITE (DC_CMD_DISPLAY_WINDOW_HEADER_0, 0x000000F0);
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DCA_WRITE (DC_WIN_A_WIN_OPTIONS_0, 0x00000000);
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DCA_WRITE (DC_WIN_A_BYTE_SWAP_0, 0x00000000);
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DCA_WRITE (DC_WIN_A_BUFFER_CONTROL_0, 0x00000000);
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DCA_WRITE (DC_WIN_A_COLOR_DEPTH_0, 0x0000000C);
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DCA_WRITE(DC_DISP_SD_LUT_0, 0x00000000); //0x54241310
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#define DC_DISP_SD_LUT_1_0 0x4c5
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#define DC_DISP_SD_LUT_2_0 0x4c6
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#define DC_DISP_SD_LUT_3_0 0x4c7
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#define DC_DISP_SD_LUT_4_0 0x4c8
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#define DC_DISP_SD_LUT_5_0 0x4c9
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#define DC_DISP_SD_LUT_6_0 0x4ca
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#define DC_DISP_SD_LUT_7_0 0x4cb
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#define DC_DISP_SD_LUT_8_0 0x4cc
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DCA_WRITE(DC_DISP_SD_LUT_1_0, 0x00000000); //0x54241314
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DCA_WRITE(DC_DISP_SD_LUT_2_0, 0x00000000); //0x54241318
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DCA_WRITE(DC_DISP_SD_LUT_3_0, 0x00000000); //0x5424131c
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DCA_WRITE(DC_DISP_SD_LUT_4_0, 0x00000000); //0x54241320
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DCA_WRITE(DC_DISP_SD_LUT_5_0, 0x00000000); //0x54241324
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DCA_WRITE(DC_DISP_SD_LUT_6_0, 0x00000000); //0x54241328
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DCA_WRITE(DC_DISP_SD_LUT_7_0, 0x00000000); //0x5424132c
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DCA_WRITE(DC_DISP_SD_LUT_8_0, 0x00000000); //0x54241330
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DCA_WRITE(DC_DISP_SD_FLICKER_CONTROL_0, 0x00000000); //0x54241334
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DCA_WRITE(DC_DISP_SD_PIXEL_COUNT_0, 0x00000000); //0x54241338
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DCA_WRITE (DC_WIN_A_POSITION_0, 0x00000000);
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DCA_WRITE (DC_WIN_A_SIZE_0, 0x00000000);
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DCA_WRITE (DC_WIN_A_PRESCALED_SIZE_0, 0x00000000);
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DCA_WRITE (DC_WIN_A_H_INITIAL_DDA_0, 0x00000000);
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DCA_WRITE (DC_WIN_A_V_INITIAL_DDA_0, 0x00000000);
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DCA_WRITE (DC_WIN_A_DDA_INCREMENT_0, 0x00000000);
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DCA_WRITE (DC_WIN_A_LINE_STRIDE_0, 0x00000000);
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DCA_WRITE (DC_WIN_A_DV_CONTROL_0, 0x00000000);
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DCA_WRITE(DC_DISP_SD_HISTOGRAM_0, 0x00000000); //0x5424133c
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#define DC_DISP_SD_HISTOGRAM_1_0 0x4d0
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#define DC_DISP_SD_HISTOGRAM_2_0 0x4d1
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#define DC_DISP_SD_HISTOGRAM_3_0 0x4d2
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#define DC_DISP_SD_HISTOGRAM_4_0 0x4d3
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#define DC_DISP_SD_HISTOGRAM_5_0 0x4d4
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#define DC_DISP_SD_HISTOGRAM_6_0 0x4d5
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#define DC_DISP_SD_HISTOGRAM_7_0 0x4d6
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DCA_WRITE(DC_DISP_SD_HISTOGRAM_1_0, 0x00000000); //0x54241340
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DCA_WRITE(DC_DISP_SD_HISTOGRAM_2_0, 0x00000000); //0x54241344
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DCA_WRITE(DC_DISP_SD_HISTOGRAM_3_0, 0x00000000); //0x54241348
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DCA_WRITE(DC_DISP_SD_HISTOGRAM_4_0, 0x00000000); //0x5424134c
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DCA_WRITE(DC_DISP_SD_HISTOGRAM_5_0, 0x00000000); //0x54241350
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DCA_WRITE(DC_DISP_SD_HISTOGRAM_6_0, 0x00000000); //0x54241354
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DCA_WRITE(DC_DISP_SD_HISTOGRAM_7_0, 0x00000000); //0x54241358
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DCA_WRITE(DC_DISP_SD_BL_PARAMETERS_0, 0x00000400); //0x5424135c
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DCA_WRITE(DC_DISP_SD_BL_TF_0, 0x00000000); //0x54241360
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#define DC_DISP_SD_BL_TF_1_0 0x4d9
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#define DC_DISP_SD_BL_TF_2_0 0x4da
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#define DC_DISP_SD_BL_TF_3_0 0x4db
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DCA_WRITE(DC_DISP_SD_BL_TF_1_0, 0x00000000); //0x54241364
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DCA_WRITE(DC_DISP_SD_BL_TF_2_0, 0x00000000); //0x54241368
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DCA_WRITE(DC_DISP_SD_BL_TF_3_0, 0x00000000); //0x5424136c
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DCA_WRITE(DC_DISP_SD_BL_CONTROL_0, 0x00000000); //0x54241370
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DCA_WRITE(DC_DISP_SD_HW_K_VALUES_0, 0x00000000); //0x54241374
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DCA_WRITE(DC_DISP_SD_MAN_K_VALUES_0, 0x00000000); //0x54241378
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DCA_WRITE(DC_DISP_SD_K_LIMIT_0, 0x00000000); //0x5424137c
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DCA_WRITE(DC_DISP_SD_WINDOW_POSITION_0, 0x00000000); //0x54241380
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DCA_WRITE(DC_DISP_SD_WINDOW_SIZE_0, 0x00000000); //0x54241384
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DCA_WRITE(DC_DISP_SD_SOFT_CLIPPING_0, 0x02000080); //0x54241388
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DCA_WRITE(DC_DISP_SD_SMOOTH_K_0, 0x00000000); //0x5424138c
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DCA_WRITE(DC_DISP_BLEND_BACKGROUND_COLOR_0, 0x00000000); //0x54241390
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DCA_WRITE(DC_DISP_INTERLACE_CONTROL_0, 0x00000000); //0x54241394
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DCA_WRITE(DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0, 0x00000000); //0x54241398
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DCA_WRITE(DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0, 0x00000000); //0x5424139c
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DCA_WRITE(DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0, 0x00000000); //0x542413a0
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DCA_WRITE(DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0, 0x00000000); //0x542413a4
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DCA_WRITE(DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0, 0x00000000); //0x542413a8
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DCA_WRITE(DC_DISP_CURSOR_UNDERFLOW_CTRL_0, 0x00000000); //0x542413ac
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DCA_WRITE(DC_DISP_CURSOR_START_ADDR_HI_0, 0x00000000); //0x542413b0
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DCA_WRITE(DC_DISP_CURSOR_START_ADDR_HI_NS_0, 0x00000000); //0x542413b4
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DCA_WRITE(DC_DISP_CURSOR_INTERLACE_CONTROL_0, 0x00000000); //0x542413b8
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DCA_WRITE(DC_DISP_CSC2_CONTROL_0, 0x00000000); //0x542413bc
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DCA_WRITE(DC_DISP_BLEND_CURSOR_CONTROL_0, 0x00000000); //0x542413c4
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DCA_WRITE(DC_DISP_DVFS_CURSOR_CONTROL_0, 0x00000003); //0x542413c8
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DCA_WRITE(DC_DISP_CURSOR_UFLOW_DBG_PIXEL_0, 0x00000000); //0x542413cc
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DCA_WRITE(DC_DISP_CURSOR_SPOOLUP_CONTROL_0, 0x00000001); //0x542413d0
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DCA_WRITE(DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0, 0x00000000); //0x542413d4
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DCA_WRITE(DC_DISP_DISPLAY_DBG_TIMING_0, 0x00000000); //0x542413d8
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DCA_WRITE(DC_DISP_DISPLAY_SPARE0_0, 0x00000000); //0x542413dc
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DCA_WRITE(DC_DISP_DISPLAY_SPARE1_0, 0x00000000); //0x542413e0
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DCA_WRITE (DC_WIN_A_BLEND_LAYER_CONTROL_0, 0x01000000);
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DCA_WRITE (DC_WIN_A_BLEND_MATCH_SELECT_0, 0x00000000);
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DCA_WRITE (DC_WIN_A_BLEND_NOMATCH_SELECT_0, 0x00000000);
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DCA_WRITE (DC_WIN_A_BLEND_ALPHA_1BIT_0, 0x00000000);
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#define wr32(reg, val) \
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WRITEL(val, (void *)reg)
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DCA_WRITE (DC_WINBUF_A_START_ADDR_HI_0, 0x00000000);
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DCA_WRITE (DC_WINBUF_A_ADDR_H_OFFSET_0, 0x00000000);
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DCA_WRITE (DC_WINBUF_A_ADDR_V_OFFSET_0, 0x00000000);
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DCA_WRITE (DC_CMD_DISPLAY_WINDOW_HEADER_0, 0x00000000);
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wr32((TEGRA_ARM_DISPLAYA + 0x0200), 0x00000000);
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wr32((TEGRA_ARM_DISPLAYA + 0x0400), 0x00000000);
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DCA_WRITE (DC_COM_CRC_CONTROL_0, 0x00000000);
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DCA_WRITE (DC_COM_CRC_CHECKSUM_0, 0x00000000);
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DCA_WRITE (DC_COM_PIN_OUTPUT_ENABLE0_0, 0x00000000);
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DCA_WRITE (DC_COM_PIN_OUTPUT_ENABLE1_0, 0x00000000);
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DCA_WRITE (DC_COM_PIN_OUTPUT_ENABLE2_0, 0x00510104);
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DCA_WRITE (DC_COM_PIN_OUTPUT_ENABLE3_0, 0x00000555);
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DCA_WRITE(DC_CMD_DISPLAY_WINDOW_HEADER_0, 0x000000F0);
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DCA_WRITE(DC_WIN_A_WIN_OPTIONS_0, 0x00000000);
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DCA_WRITE(DC_WIN_A_BYTE_SWAP_0, 0x00000000);
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DCA_WRITE(DC_WIN_A_BUFFER_CONTROL_0, 0x00000000);
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DCA_WRITE(DC_WIN_A_COLOR_DEPTH_0, 0x0000000C);
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DCA_WRITE(DC_WIN_A_POSITION_0, 0x00000000);
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DCA_WRITE(DC_WIN_A_SIZE_0, 0x00000000);
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DCA_WRITE(DC_WIN_A_PRESCALED_SIZE_0, 0x00000000);
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DCA_WRITE(DC_WIN_A_H_INITIAL_DDA_0, 0x00000000);
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DCA_WRITE(DC_WIN_A_V_INITIAL_DDA_0, 0x00000000);
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DCA_WRITE(DC_WIN_A_DDA_INCREMENT_0, 0x00000000);
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DCA_WRITE(DC_WIN_A_LINE_STRIDE_0, 0x00000000);
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DCA_WRITE(DC_WIN_A_DV_CONTROL_0, 0x00000000);
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DCA_WRITE(DC_WIN_A_BLEND_LAYER_CONTROL_0, 0x01000000);
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DCA_WRITE(DC_WIN_A_BLEND_MATCH_SELECT_0, 0x00000000);
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DCA_WRITE(DC_WIN_A_BLEND_NOMATCH_SELECT_0, 0x00000000);
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DCA_WRITE(DC_WIN_A_BLEND_ALPHA_1BIT_0, 0x00000000);
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DCA_WRITE(DC_WINC_A_PALETTE_COLOR_EXT_0, 0x00000000);
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DCA_WRITE(DC_WINC_A_CSC_YOF_0, 0x00000000);
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DCA_WRITE(DC_WINC_A_CSC_KYRGB_0, 0x00000000);
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DCA_WRITE(DC_WINC_A_CSC_KUR_0, 0x00000000);
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DCA_WRITE(DC_WINC_A_CSC_KVR_0, 0x00000000);
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DCA_WRITE(DC_WINC_A_CSC_KUG_0, 0x00000000);
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DCA_WRITE(DC_WINC_A_CSC_KVG_0, 0x00000000);
|
||||
DCA_WRITE(DC_WINC_A_CSC_KUB_0, 0x00000000);
|
||||
DCA_WRITE(DC_WINC_A_CSC_KVB_0, 0x00000000);
|
||||
DCA_WRITE(DC_WINBUF_A_START_ADDR_HI_0, 0x00000000);
|
||||
DCA_WRITE(DC_WINBUF_A_ADDR_H_OFFSET_0, 0x00000000);
|
||||
DCA_WRITE(DC_WINBUF_A_ADDR_V_OFFSET_0, 0x00000000);
|
||||
DCA_WRITE(DC_CMD_DISPLAY_WINDOW_HEADER_0, 0x00000000);
|
||||
|
||||
DCA_WRITE(DC_COM_CRC_CONTROL_0, 0x00000000); //0x54240c00
|
||||
DCA_WRITE(DC_COM_CRC_CHECKSUM_0, 0x00000000); //0x54240c04
|
||||
DCA_WRITE(DC_COM_PIN_OUTPUT_ENABLE0_0, 0x00000000); //0x54240c08
|
||||
DCA_WRITE(DC_COM_PIN_OUTPUT_ENABLE1_0, 0x00000000); //0x54240c0c
|
||||
DCA_WRITE(DC_COM_PIN_OUTPUT_ENABLE2_0, 0x00510104); //0x54240c10
|
||||
DCA_WRITE(DC_COM_PIN_OUTPUT_ENABLE3_0, 0x00000555); //0x54240c14
|
||||
DCA_WRITE(DC_COM_PIN_OUTPUT_POLARITY0_0, 0x00000000); //0x54240c18
|
||||
DCA_WRITE(DC_COM_PIN_OUTPUT_POLARITY1_0, 0x00000000); //0x54240c1c
|
||||
DCA_WRITE(DC_COM_PIN_OUTPUT_POLARITY2_0, 0x00000000); //0x54240c20
|
||||
DCA_WRITE(DC_COM_PIN_OUTPUT_POLARITY3_0, 0x00000000); //0x54240c24
|
||||
DCA_WRITE(DC_COM_PIN_OUTPUT_DATA0_0, 0x00000000); //0x54240c28
|
||||
DCA_WRITE(DC_COM_PIN_OUTPUT_DATA1_0, 0x00000000); //0x54240c2c
|
||||
DCA_WRITE(DC_COM_PIN_OUTPUT_DATA2_0, 0x00000000); //0x54240c30
|
||||
DCA_WRITE(DC_COM_PIN_OUTPUT_DATA3_0, 0x00000000); //0x54240c34
|
||||
DCA_WRITE(DC_COM_PIN_INPUT_DATA0_0, 0x00000000); //0x54240c48
|
||||
DCA_WRITE(DC_COM_PIN_INPUT_DATA1_0, 0x00000000); //0x54240c4c
|
||||
DCA_WRITE(DC_COM_PIN_OUTPUT_SELECT0_0, 0x00000000); //0x54240c50
|
||||
DCA_WRITE(DC_COM_PIN_OUTPUT_SELECT1_0, 0x00000000); //0x54240c54
|
||||
DCA_WRITE(DC_COM_PIN_OUTPUT_SELECT2_0, 0x00000000); //0x54240c58
|
||||
DCA_WRITE(DC_COM_PIN_OUTPUT_SELECT3_0, 0x00000000); //0x54240c5c
|
||||
DCA_WRITE(DC_COM_PIN_OUTPUT_SELECT4_0, 0x00000000); //0x54240c60
|
||||
DCA_WRITE(DC_COM_PIN_OUTPUT_SELECT5_0, 0x00000000); //0x54240c64
|
||||
DCA_WRITE(DC_COM_PIN_OUTPUT_SELECT6_0, 0x00000000); //0x54240c68
|
||||
DCA_WRITE(DC_COM_PIN_MISC_CONTROL_0, 0x00000000); //0x54240c6c
|
||||
DCA_WRITE(DC_COM_PM0_CONTROL_0, 0x00000000); //0x54240c70
|
||||
DCA_WRITE(DC_COM_PM0_DUTY_CYCLE_0, 0x00000000); //0x54240c74
|
||||
DCA_WRITE(DC_COM_PM1_CONTROL_0, 0x00000000); //0x54240c78
|
||||
DCA_WRITE(DC_COM_PM1_DUTY_CYCLE_0, 0x00000000); //0x54240c7c
|
||||
DCA_WRITE(DC_COM_SPI_CONTROL_0, 0x00000000); //0x54240c80
|
||||
DCA_WRITE(DC_COM_SPI_START_BYTE_0, 0x00000000); //0x54240c84
|
||||
DCA_WRITE(DC_COM_HSPI_WRITE_DATA_AB_0, 0x00000000); //0x54240c88
|
||||
DCA_WRITE(DC_COM_HSPI_WRITE_DATA_CD_0, 0x00000000); //0x54240c8c
|
||||
DCA_WRITE(DC_COM_HSPI_CS_DC_0, 0x00000000); //0x54240c90
|
||||
DCA_WRITE(DC_COM_SCRATCH_REGISTER_A_0, 0x00000000); //0x54240c94
|
||||
DCA_WRITE(DC_COM_SCRATCH_REGISTER_B_0, 0x00000000); //0x54240c98
|
||||
DCA_WRITE(DC_COM_CRC_CHECKSUM_LATCHED_0, 0x00000000); //0x54240ca4
|
||||
DCA_WRITE(DC_COM_CMU_CSC_KRR_0, 0x00000000); //0x54240ca8
|
||||
DCA_WRITE(DC_COM_CMU_CSC_KGR_0, 0x00000000); //0x54240cac
|
||||
DCA_WRITE(DC_COM_CMU_CSC_KBR_0, 0x00000000); //0x54240cb0
|
||||
DCA_WRITE(DC_COM_CMU_CSC_KRG_0, 0x00000000); //0x54240cb4
|
||||
DCA_WRITE(DC_COM_CMU_CSC_KGG_0, 0x00000000); //0x54240cb8
|
||||
DCA_WRITE(DC_COM_CMU_CSC_KBG_0, 0x00000000); //0x54240cbc
|
||||
DCA_WRITE(DC_COM_CMU_CSC_KRB_0, 0x00000000); //0x54240cc0
|
||||
DCA_WRITE(DC_COM_CMU_CSC_KGB_0, 0x00000000); //0x54240cc4
|
||||
DCA_WRITE(DC_COM_CMU_CSC_KBB_0, 0x00000000); //0x54240cc8
|
||||
DCA_WRITE(DC_COM_CMU_LUT_MASK_0, 0x00000000); //0x54240ccc
|
||||
DCA_WRITE(DC_COM_CMU_LUT1_0, 0x00000000); //0x54240cd8
|
||||
DCA_WRITE(DC_COM_CMU_LUT2_0, 0x00000000); //0x54240cdc
|
||||
DCA_WRITE(DC_COM_CMU_LUT1_READ_0, 0x00000000); //0x54240ce0
|
||||
DCA_WRITE(DC_COM_CMU_LUT2_READ_0, 0x00000000); //0x54240ce4
|
||||
DCA_WRITE(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0, 0x00000000); //0x54240004
|
||||
DCA_WRITE(DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0, 0x00000000); //0x54240008
|
||||
DCA_WRITE(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0, 0x00000000); //0x54240024
|
||||
DCA_WRITE(DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0, 0x00000000); //0x54240028
|
||||
DCA_WRITE(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0, 0x00000000); //0x54240044
|
||||
DCA_WRITE(DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0, 0x00000000); //0x54240048
|
||||
DCA_WRITE(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0, 0x00000000); //0x54240064
|
||||
DCA_WRITE(DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0, 0x00000000); //0x54240068
|
||||
DCA_WRITE(DC_CMD_CONT_SYNCPT_VSYNC_0, 0x00000000); //0x542400a0
|
||||
DCA_WRITE(DC_CMD_DISPLAY_COMMAND_OPTION0_0, 0x00000000); //0x542400c4
|
||||
DCA_WRITE(DC_CMD_DISPLAY_COMMAND_0, 0x00000000); //0x542400c8
|
||||
DCA_WRITE(DC_CMD_SIGNAL_RAISE_0, 0x00000000); //0x542400cc
|
||||
DCA_WRITE(DC_CMD_DISPLAY_POWER_CONTROL_0, 0x00000000); //0x542400d8
|
||||
DCA_WRITE(DC_CMD_SIGNAL_RAISE1_0, 0x00000000); //0x542400f0
|
||||
DCA_WRITE(DC_CMD_SIGNAL_RAISE2_0, 0x00000000); //0x542400f4
|
||||
DCA_WRITE(DC_CMD_SIGNAL_RAISE3_0, 0x00000000); //0x542400f8
|
||||
DCA_WRITE(DC_CMD_STATE_CONTROL_0, 0x00000000); //0x54240104
|
||||
DCA_WRITE(DC_CMD_DISPLAY_WINDOW_HEADER_0, 0x00000000); //0x54240108
|
||||
DCA_WRITE(DC_CMD_REG_ACT_CONTROL_0, 0x00000000); //0x5424010c
|
||||
DCA_WRITE(DC_CMD_WIN_T_STATE_CONTROL_0, 0x00000000); //0x54240110
|
||||
DCA_WRITE(DC_CMD_SECURE_CONTROL_0, 0x00000000); //0x54240114
|
||||
DCA_WRITE(DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0, 0x00000000); //0x54240134
|
||||
DCA_WRITE(DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0, 0x00000000); //0x54240138
|
||||
printk(BIOS_SPEW, "initial DCA done\n");
|
||||
}
|
||||
|
||||
|
|
@ -375,119 +141,6 @@ void init_sor_regs(void)
|
|||
WRITEL(_reg_val, (void *)(TEGRA_ARM_SOR + (reg<<2))); \
|
||||
}
|
||||
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_SUPER_STATE0_0, 0x00000000); //0x54540004
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_SUPER_STATE1_0, 0x00000000); //0x54540008
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_STATE0_0, 0x00000000); //0x5454000c
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_STATE1_0, 0x00000040); //0x54540010
|
||||
SOR_WRITE(SOR_NV_PDISP_HEAD_STATE0, 0x00000000); //0x54540014
|
||||
SOR_WRITE(SOR_NV_PDISP_HEAD_STATE0_1, 0x00000000); //0x54540018
|
||||
SOR_WRITE(SOR_NV_PDISP_HEAD_STATE1, 0x01011000); //0x5454001c
|
||||
SOR_WRITE(SOR_NV_PDISP_HEAD_STATE1_1, 0x01011000); //0x54540020
|
||||
SOR_WRITE(SOR_NV_PDISP_HEAD_STATE2, 0x00000001); //0x54540024
|
||||
SOR_WRITE(SOR_NV_PDISP_HEAD_STATE2_1, 0x00000001); //0x54540028
|
||||
SOR_WRITE(SOR_NV_PDISP_HEAD_STATE3, 0x00010011); //0x5454002c
|
||||
SOR_WRITE(SOR_NV_PDISP_HEAD_STATE3_1, 0x00010011); //0x54540030
|
||||
SOR_WRITE(SOR_NV_PDISP_HEAD_STATE4, 0x00110100); //0x54540034
|
||||
SOR_WRITE(SOR_NV_PDISP_HEAD_STATE4_1, 0x00110100); //0x54540038
|
||||
SOR_WRITE(SOR_NV_PDISP_HEAD_STATE5, 0x00000001); //0x5454003c
|
||||
SOR_WRITE(SOR_NV_PDISP_HEAD_STATE5_1, 0x00000001); //0x54540040
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_CRC_CNTRL_0, 0x00000000); //0x54540044
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0, 0x00000000); //0x54540048
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_CLK_CNTRL_0, 0x00000018); //0x5454004c
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_CAP_0, 0x00000000); //0x54540050
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_PWR_0, 0x00000000); //0x54540054
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_TEST_0, 0x00800000); //0x54540058
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_PLL0_0, 0x0f0003d5); //0x5454005c
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_PLL1_0, 0x00001000); //0x54540060
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_PLL2_0, 0x01c00000); //0x54540064
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_PLL3_0, 0x38002220); //0x54540068
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_CSTM_0, 0x0001c800); //0x5454006c
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_LVDS_0, 0x0001c800); //0x54540070
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_CRCA_0, 0x00000000); //0x54540074
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_CRCB_0, 0x00000000); //0x54540078
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_BLANK_0, 0x00000000); //0x5454007c
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_CTL_0, 0x00008800); //0x54540080
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0, 0x00011000); //0x54540084
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST0_0, 0x01008000); //0x54540088
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST1_0, 0x01008000); //0x5454008c
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST2_0, 0x01008000); //0x54540090
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST3_0, 0x01008000); //0x54540094
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST4_0, 0x01008000); //0x54540098
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST5_0, 0x01008000); //0x5454009c
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST6_0, 0x01008000); //0x545400a0
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST7_0, 0x01008000); //0x545400a4
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST8_0, 0x01008000); //0x545400a8
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST9_0, 0x01008000); //0x545400ac
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INSTA_0, 0x01008000); //0x545400b0
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INSTB_0, 0x01008000); //0x545400b4
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INSTC_0, 0x01008000); //0x545400b8
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INSTD_0, 0x01008000); //0x545400bc
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INSTE_0, 0x01008000); //0x545400c0
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INSTF_0, 0x01008000); //0x545400c4
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_PWM_DIV_0, 0x00000000); //0x545400c8
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_PWM_CTL_0, 0x00000000); //0x545400cc
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_VCRCA0_0, 0x00000000); //0x545400d0
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_VCRCA1_0, 0x00000000); //0x545400d4
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_VCRCB0_0, 0x00000000); //0x545400d8
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_VCRCB1_0, 0x00000000); //0x545400dc
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_CCRCA0_0, 0x00000000); //0x545400e0
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_CCRCA1_0, 0x00000000); //0x545400e4
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_CCRCB0_0, 0x00000000); //0x545400e8
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_CCRCB1_0, 0x00000000); //0x545400ec
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_EDATAA0_0, 0x00000000); //0x545400f0
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_EDATAA1_0, 0x00000000); //0x545400f4
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_EDATAB0_0, 0x00000000); //0x545400f8
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_EDATAB1_0, 0x00000000); //0x545400fc
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_COUNTA0_0, 0x00000000); //0x54540100
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_COUNTA1_0, 0x00000000); //0x54540104
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_COUNTB0_0, 0x00000000); //0x54540108
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_COUNTB1_0, 0x00000000); //0x5454010c
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DEBUGA0_0, 0x00000000); //0x54540110
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DEBUGA1_0, 0x00000000); //0x54540114
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DEBUGB0_0, 0x00000000); //0x54540118
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DEBUGB1_0, 0x00000000); //0x5454011c
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_TRIG_0, 0x00000000); //0x54540120
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_MSCHECK_0, 0x80000000); //0x54540124
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_XBAR_CTRL_0, 0x8d111a23); //0x54540128
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_XBAR_POL_0, 0x00000000); //0x5454012c
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_LINKCTL0_0, 0x00000100); //0x54540130
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_LINKCTL1_0, 0x00000100); //0x54540134
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0, 0x40404040); //0x54540138
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0, 0x80808080); //0x5454013c
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0, 0x00000040); //0x54540140
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0, 0x00000080); //0x54540144
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0, 0x00000000); //0x54540148
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0, 0x00000000); //0x5454014c
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0, 0x00000000); //0x54540150
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0, 0x00000000); //0x54540154
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_POSTCURSOR0_0, 0x00000000); //0x54540158
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_POSTCURSOR1_0, 0x00000000); //0x5454015c
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_CONFIG0_0, 0x94000000); //0x54540160
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_CONFIG1_0, 0x94000000); //0x54540164
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_MN0_0, 0x00008000); //0x54540168
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_MN1_0, 0x00008000); //0x5454016c
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_PADCTL0_0, 0x00800000); //0x54540170
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_PADCTL1_0, 0x00000000); //0x54540174
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_DEBUG0_0, 0x00000000); //0x54540178
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_DEBUG1_0, 0x00000000); //0x5454017c
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_SPARE0_0, 0x00000002); //0x54540180
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_SPARE1_0, 0x00000000); //0x54540184
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0, 0x001f0001); //0x54540188
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0, 0x00000000); //0x5454018c
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0, 0x00000000); //0x54540190
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0, 0x00000000); //0x54540194
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0,0x00000000); //0x54540198
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0,0x00000000); //0x5454019c
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0,0x00000000); //0x545401a0
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0,0x00000000); //0x545401a4
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0,0x00000000); //0x545401a8
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0,0x00000000); //0x545401ac
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0,0x00000000); //0x545401b0
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_TPG_0, 0x50505050); //0x545401b4
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0, 0x00000000); //0x545401b8
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0, 0x00000000); //0x545401bc
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0, 0x00000000); //0x545401c0
|
||||
SOR_WRITE(SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0, 0x00000000); //0x545401c4
|
||||
printk(BIOS_SPEW, "initial SOR done\n");
|
||||
}
|
||||
|
||||
|
|
@ -514,29 +167,6 @@ void init_dpaux_regs(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
DPAUX_WRITE(DPAUX_INTR_EN_AUX, 0x00000000); //0x545c0004
|
||||
DPAUX_WRITE(DPAUX_INTR_AUX, 0x00000000); //0x545c0014
|
||||
DPAUX_WRITE(DPAUX_DP_AUXDATA_WRITE_W0, 0x00000000); //0x545c0024
|
||||
DPAUX_WRITE(DPAUX_DP_AUXDATA_WRITE_W1, 0x00000000); //0x545c0034
|
||||
DPAUX_WRITE(DPAUX_DP_AUXDATA_WRITE_W2, 0x00000000); //0x545c0044
|
||||
DPAUX_WRITE(DPAUX_DP_AUXDATA_WRITE_W3, 0x00000000); //0x545c0054
|
||||
DPAUX_WRITE(DPAUX_DP_AUXDATA_READ_W0, 0x00000000); //0x545c0064
|
||||
DPAUX_WRITE(DPAUX_DP_AUXDATA_READ_W1, 0x00000000); //0x545c0074
|
||||
DPAUX_WRITE(DPAUX_DP_AUXDATA_READ_W2, 0x00000000); //0x545c0084
|
||||
DPAUX_WRITE(DPAUX_DP_AUXDATA_READ_W3, 0x00000000); //0x545c0094
|
||||
DPAUX_WRITE(DPAUX_DP_AUXADDR, 0x00000000); //0x545c00a4
|
||||
DPAUX_WRITE(DPAUX_DP_AUXCTL, 0x00000000); //0x545c00b4
|
||||
DPAUX_WRITE(DPAUX_DP_AUXSTAT, 0x10000000); //0x545c00c4
|
||||
DPAUX_WRITE(DPAUX_DP_AUX_SINKSTATLO, 0x00000000); //0x545c00d4
|
||||
DPAUX_WRITE(DPAUX_DP_AUX_SINKSTATHI, 0x00000000); //0x545c00e4
|
||||
DPAUX_WRITE(DPAUX_HPD_CONFIG, 0x07d000fa); //0x545c00f4
|
||||
DPAUX_WRITE(DPAUX_HPD_IRQ_CONFIG, 0x000000fa); //0x545c0104
|
||||
DPAUX_WRITE(DPAUX_DP_AUX_CONFIG, 0x00000190); //0x545c0114
|
||||
DPAUX_WRITE(DPAUX_HYBRID_PADCTL, 0x00002462); //0x545c0124
|
||||
DPAUX_WRITE(DPAUX_HYBRID_SPARE, 0x00000000); //0x545c0134
|
||||
DPAUX_WRITE(DPAUX_SCRATCH_REG0_0, 0x00000000); //0x545c0144
|
||||
DPAUX_WRITE(DPAUX_SCRATCH_REG1_0, 0x00000000); //0x545c0154
|
||||
DPAUX_WRITE(DPAUX_SCRATCH_REG2_0, 0x00000000); //0x545c0164
|
||||
printk(BIOS_SPEW, "initial DPAUX done\n");
|
||||
}
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -17,6 +17,166 @@
|
|||
#ifndef __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_DISPLAY_H__
|
||||
#define __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_DISPLAY_H__
|
||||
|
||||
/* ardisplay.h */
|
||||
#define DC_CMD_DISPLAY_WINDOW_HEADER_0 0x42
|
||||
#define DC_COM_CRC_CONTROL_0 0x300
|
||||
#define DC_COM_CRC_CHECKSUM_0 0x301
|
||||
#define DC_COM_PIN_OUTPUT_ENABLE0_0 0x302
|
||||
#define DC_COM_PIN_OUTPUT_ENABLE1_0 0x303
|
||||
#define DC_COM_PIN_OUTPUT_ENABLE2_0 0x304
|
||||
#define DC_COM_PIN_OUTPUT_ENABLE3_0 0x305
|
||||
#define DC_CMD_STATE_ACCESS_0 0x40
|
||||
#define DC_DISP_DISP_CLOCK_CONTROL_0 0x42e
|
||||
#define DC_DISP_DISP_TIMING_OPTIONS_0 0x405
|
||||
#define DC_DISP_REF_TO_SYNC_0 0x406
|
||||
#define DC_DISP_SYNC_WIDTH_0 0x407
|
||||
#define DC_DISP_BACK_PORCH_0 0x408
|
||||
#define DC_DISP_DISP_ACTIVE_0 0x409
|
||||
#define DC_DISP_FRONT_PORCH_0 0x40a
|
||||
#define DC_DISP_DISP_WIN_OPTIONS_0 0x402
|
||||
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_SHIFT 25
|
||||
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_FIELD (0x1 << DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_SHIFT)
|
||||
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0 0x400
|
||||
#define DC_DISP_BLEND_BACKGROUND_COLOR_0 0x4e4
|
||||
#define DC_CMD_DISPLAY_COMMAND_0 0x32
|
||||
#define DC_CMD_STATE_CONTROL_0 0x41
|
||||
#define DC_CMD_DISPLAY_POWER_CONTROL_0 0x36
|
||||
|
||||
/* ardisplay_a.h */
|
||||
#define DC_WIN_A_WIN_OPTIONS_0 0x700
|
||||
#define DC_WIN_A_BYTE_SWAP_0 0x701
|
||||
#define DC_WIN_A_BUFFER_CONTROL_0 0x702
|
||||
#define DC_WIN_A_COLOR_DEPTH_0 0x703
|
||||
#define DC_WIN_A_POSITION_0 0x704
|
||||
#define DC_WIN_A_SIZE_0 0x705
|
||||
#define DC_WIN_A_PRESCALED_SIZE_0 0x706
|
||||
#define DC_WIN_A_H_INITIAL_DDA_0 0x707
|
||||
#define DC_WIN_A_V_INITIAL_DDA_0 0x708
|
||||
#define DC_WIN_A_DDA_INCREMENT_0 0x709
|
||||
#define DC_WIN_A_LINE_STRIDE_0 0x70a
|
||||
#define DC_WIN_A_DV_CONTROL_0 0x70e
|
||||
#define DC_WIN_A_BLEND_LAYER_CONTROL_0 0x716
|
||||
#define DC_WIN_A_BLEND_MATCH_SELECT_0 0x717
|
||||
#define DC_WIN_A_BLEND_NOMATCH_SELECT_0 0x718
|
||||
#define DC_WIN_A_BLEND_ALPHA_1BIT_0 0x719
|
||||
#define DC_WINBUF_A_START_ADDR_HI_0 0x80d
|
||||
#define DC_WINBUF_A_ADDR_H_OFFSET_0 0x806
|
||||
#define DC_WINBUF_A_ADDR_V_OFFSET_0 0x808
|
||||
|
||||
/* ardisplay_bd.h */
|
||||
#define DC_B_WIN_BD_SIZE_0 0xd85
|
||||
#define DC_B_WIN_BD_PRESCALED_SIZE_0 0xd86
|
||||
#define DC_B_WIN_BD_LINE_STRIDE_0 0xd8a
|
||||
#define DC_B_WIN_BD_COLOR_DEPTH_0 0xd83
|
||||
#define DC_B_WINBUF_BD_START_ADDR_0 0xdc0
|
||||
#define DC_B_WIN_BD_DDA_INCREMENT_0 0xd89
|
||||
#define DC_B_WIN_BD_WIN_OPTIONS_0 0xd80
|
||||
#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_SHIFT 30
|
||||
#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_FIELD (0x1 << DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_SHIFT)
|
||||
#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_ENABLE (1)
|
||||
|
||||
/* arsor.h */
|
||||
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0 0x13
|
||||
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0 0x5c
|
||||
#define SOR_NV_PDISP_SOR_PLL0_0 0x17
|
||||
#define SOR_NV_PDISP_SOR_PLL1_0 0x18
|
||||
#define SOR_NV_PDISP_SOR_PLL2_0 0x19
|
||||
#define SOR_NV_PDISP_SOR_PLL3_0 0x1a
|
||||
#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_SHIFT 22
|
||||
#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL2_0_AUX6_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_PLL0_0_PWR_SHIFT 0
|
||||
#define SOR_NV_PDISP_SOR_PLL0_0_PWR_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL0_0_PWR_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_SHIFT 2
|
||||
#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL0_0_VCOPD_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_SHIFT 24
|
||||
#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL2_0_AUX8_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_SHIFT 23
|
||||
#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL2_0_AUX7_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_SHIFT 25
|
||||
#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL2_0_AUX9_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0 0x4e
|
||||
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0 0x52
|
||||
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0 0x56
|
||||
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0 0x5c
|
||||
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_SHIFT 8
|
||||
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_FIELD (0xff << SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_SHIFT 22
|
||||
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_FIELD (0x1 << SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_LVDS_0 0x1c
|
||||
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0 0x13
|
||||
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0 0x4c
|
||||
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0 0x21
|
||||
#define SOR_NV_PDISP_SOR_DP_TPG_0 0x6d
|
||||
#define SOR_NV_PDISP_HEAD_STATE1_0 0x7
|
||||
#define SOR_NV_PDISP_HEAD_STATE2_0 0x9
|
||||
#define SOR_NV_PDISP_HEAD_STATE3_0 0xb
|
||||
#define SOR_NV_PDISP_HEAD_STATE4_0 0xd
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0 0x4
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_SHIFT 12
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_FIELD (0x1 << SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_SHIFT 13
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_FIELD (0x1 << SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_SHIFT 8
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_FIELD (0xf << SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_LVDS_CUSTOM (0)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_DP_A (8)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_DP_B (9)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_CUSTOM (15)
|
||||
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_ACTIVE_RASTER (0)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_COMPLETE_RASTER (1)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_NON_ACTIVE_RASTER (2)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_SHIFT 6
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_FIELD (0x3 << SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SHIFT 4
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_FIELD (0x3 << SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_NONE (0)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SUBHEAD0 (1)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SUBHEAD1 (2)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_BOTH (3)
|
||||
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_SHIFT 0
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_FIELD (0xf << SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_NONE (0)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_HEAD0 (1)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_HEAD1 (2)
|
||||
|
||||
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0 0x58
|
||||
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_SHIFT 24
|
||||
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_FIELD (0x1 << SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_SHIFT 16
|
||||
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_FIELD (0xf << SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_SHIFT 8
|
||||
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_FIELD (0x7f << SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_SHIFT 0
|
||||
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_FIELD (0x3f << SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_SHIFT 2
|
||||
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_FIELD (0x7f << SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_SHIFT)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_SHIFT 17
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_FIELD (0xf << SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_SHIFT)
|
||||
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_DEFAULTVAL (0)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_16_422 (1)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_18_444 (2)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_20_422 (3)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_24_422 (4)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_24_444 (5)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_30_444 (6)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_32_422 (7)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_36_444 (8)
|
||||
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_48_444 (9)
|
||||
|
||||
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0 0x11
|
||||
#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0 0x64
|
||||
#define SOR_NV_PDISP_SOR_DP_SPARE0_0 0x60
|
||||
#define SOR_NV_PDISP_SOR_PWR_0 0x15
|
||||
#define SOR_NV_PDISP_SOR_STATE0_0 0x3
|
||||
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0 0x2
|
||||
#define SOR_NV_PDISP_SOR_SUPER_STATE0_0 0x1
|
||||
|
||||
/* ardpaux.h */
|
||||
#define DPAUX_DP_AUXDATA_READ_W0 0x19
|
||||
|
||||
void setup_display(struct soc_nvidia_tegra124_config *config);
|
||||
void init_dca_regs(void);
|
||||
void init_dpaux_regs(void);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue