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Tegra124: SDMMC: Take the SDMMC 3 and 4 out of reset and ungate their clocks.

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These are attached to the SD card and the EMMC on nyan.

BUG=None
TEST=Built and booted into depthcharge on nyan. With changes that configure
these controllers there, saw the driver attempt (and fail) to read data from
the device instead of just hanging.
BRANCH=None

Change-Id: Idf82adc9e8708388d2ad77fca00e224af0fe7661
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/173793
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
This commit is contained in:
Gabe Black 2013-10-19 03:53:42 -07:00 • committed by chrome-internal-fetch
commit c238b87bcd
1 changed files with 8 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

12
src/soc/nvidia/tegra124/clock.c
View file

@ -266,11 +266,13 @@ void clock_config(void)
{
/* Enable clocks for the required peripherals. */
setbits_le32(&clk_rst->clk_out_enb_l,
CLK_L_CACHE2 | CLK_L_GPIO | CLK_L_TMR | CLK_L_I2C1);
CLK_L_CACHE2 | CLK_L_GPIO | CLK_L_TMR | CLK_L_I2C1 |
CLK_L_SDMMC4);
setbits_le32(&clk_rst->clk_out_enb_h,
CLK_H_EMC | CLK_H_I2C2 | CLK_H_I2C5 | CLK_H_SBC1 |
CLK_H_PMC | CLK_H_APBDMA | CLK_H_MEM);
setbits_le32(&clk_rst->clk_out_enb_u, CLK_U_I2C3 | CLK_U_CSITE);
setbits_le32(&clk_rst->clk_out_enb_u,
CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3);
setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_MSELECT);
setbits_le32(&clk_rst->clk_out_enb_w, CLK_W_DVFS);
@ -300,11 +302,13 @@ void clock_config(void)
/* Take required peripherals out of reset. */
clrbits_le32(&clk_rst->rst_dev_l,
CLK_L_CACHE2 | CLK_L_GPIO | CLK_L_TMR | CLK_L_I2C1);
CLK_L_CACHE2 | CLK_L_GPIO | CLK_L_TMR | CLK_L_I2C1 |
CLK_L_SDMMC4);
clrbits_le32(&clk_rst->rst_dev_h,
CLK_H_EMC | CLK_H_I2C2 | CLK_H_I2C5 | CLK_H_SBC1 |
CLK_H_PMC | CLK_H_APBDMA | CLK_H_MEM);
clrbits_le32(&clk_rst->rst_dev_u, CLK_U_I2C3 | CLK_U_CSITE);
clrbits_le32(&clk_rst->rst_dev_u,
CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3);
clrbits_le32(&clk_rst->rst_dev_v, CLK_V_MSELECT);
clrbits_le32(&clk_rst->rst_dev_w, CLK_W_DVFS);
}