erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

broadwell: Do not reserve SMM relocation region

Browse source 
In order to not mess up legacy bootloaders do not reserve the
SMM relocation region but instead backup and restore the contents
during CPU init and SMM relocation.

BUG=chrome-os-partner:28234
TEST=None

Change-Id: Icc939d454dd8f3a5a6db917a8a96e3800ebdb1bc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199402
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2014-05-02 14:56:56 -07:00 • committed by chrome-internal-fetch
commit e2ab52340e
2 changed files with 11 additions and 23 deletions
Download patch file Download diff file Expand all files Collapse all files

7
src/soc/intel/broadwell/cpu.c
View file

@ -676,6 +676,7 @@ void broadwell_init_cpus(device_t dev)
int num_cores;
msr_t msr;
struct mp_params mp_params;
void *smm_save_area;
msr = rdmsr(CORE_THREAD_COUNT_MSR);
num_threads = (msr.lo >> 0) & 0xffff;
@ -692,6 +693,9 @@ void broadwell_init_cpus(device_t dev)
microcode_patch = intel_microcode_find();
/* Save default SMM area before relocation occurs. */
smm_save_area = backup_default_smm_area();
mp_params.num_cpus = num_threads;
mp_params.parallel_microcode_load = 1;
if (ht_disabled)
@ -710,6 +714,9 @@ void broadwell_init_cpus(device_t dev)
printk(BIOS_ERR, "MP initialization failure.\n");
}
/* Restore the default SMM region. */
restore_default_smm_area(smm_save_area);
/* Enable ROM caching if option was selected. */
x86_mtrr_enable_rom_caching();
}

27
src/soc/intel/broadwell/systemagent.c
View file

@ -285,10 +285,7 @@ static void mc_add_dram_resources(device_t dev)
/*
* These are the host memory ranges that should be added:
* - 0 -> SMM_DEFAULT_BASE : cacheable
* - SMM_DEFAULT_BASE -> SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE :
* cacheable and reserved
* - SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE -> 0xa0000 : cacheable
* - 0 -> 0xa0000: cacheable
* - 0xc0000 -> TSEG : cacheable
* - TESG -> BGSM: cacheable with standard MTRRs and reserved
* - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved
@ -318,21 +315,8 @@ static void mc_add_dram_resources(device_t dev)
*/
index = 0;
/* 0 - > SMM_DEFAULT_BASE */
/* 0 - > 0xa0000 */
base_k = 0;
size_k = SMM_DEFAULT_BASE >> 10;
ram_resource(dev, index++, base_k, size_k);
/* SMM_DEFAULT_BASE -> SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE */
resource = new_resource(dev, index++);
resource->base = SMM_DEFAULT_BASE;
resource->size = SMM_DEFAULT_SIZE;
resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
IORESOURCE_CACHEABLE | IORESOURCE_STORED |
IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
/* SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE -> 0xa0000 */
base_k = (SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE) >> 10;
size_k = (0xa0000 >> 10) - base_k;
ram_resource(dev, index++, base_k, size_k);
@ -372,11 +356,8 @@ static void mc_add_dram_resources(device_t dev)
mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
reserved_ram_resource(dev, index++, (0xc0000 >> 10),
(0x100000 - 0xc0000) >> 10);
#if CONFIG_CHROMEOS_RAMOOPS
reserved_ram_resource(dev, index++,
CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);
#endif
chromeos_reserve_ram_oops(dev, index++);
}
static void systemagent_read_resources(device_t dev)