Now that the ACP device is always present in DSDT move the
MSG0 method and helper functions into DSDT. This allows to clean
the common ACP code and reduces differences in the runtime code
pathes. The newly introduced DSDT is also verified at compile time.
Change-Id: Ifc55278aa66abcb54691017738cc843e3088d8e8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91159
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the ACP ACPI device called ACPD from SSDT to DSDT so that a SoC
or a mainboard DSDT can extend the ACP configuration.
Therefore, drop acpi_device_write_pci_dev() in SSDT. Introduce a STAT
variable in ASL, which defaults to 3 (present, enabled, hidden, not ok)
when the device is set to "off" in the devicetree.cb, since the PCI
device is not actual disabled by FSP. When not disabled in devicetree.cb,
STAT will be overriden in SSDT with the actual device status. The STAT
variable is returned by _STA method.
The ACP child devices where seen on Phoenix and KrackenPoint and not
seen on Rembrandt, Cezanne or Mendocino.
Assume older platforms do not have ACP child devices in ACPI.
TEST=Booted on AMD birman_plus (glinda) and verified ACP is working.
TEST=Set ACP device to off and verified it's marked hidden on Windows 11
Device Manager.
Change-Id: I31c3f01f83f27d0121f9e003e60a7f12d49427f6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Commit 91a1276d53 ("soc/intel/alderlake: Implement WA for DDR5 DIMM
modules") was added to allow FSP to perform the SPD read for DDR5
modules since coreboot did not properly support reading SPD from
EEPROM for DDR5. The same code is copied here for Pantherlake.
BUG=None
TEST=Build fatcat and verify there are no errors
Change-Id: Iacd43774c227fae5edc309dc1e163cc5c87160e4
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91202
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch applies commit 0e7cf3d81d ("soc/intel/alderlake: Fix DDR5
channel mapping") to PantherLake.
DDR5 memory modules have two separate 32-bit channels (40-bit on ECC
memory modules), and the SPD info refers to one channel: the primary
bus width is 32 (or 40) bits and the "DIMM size" is halved. On Panther
Lake, there are 2 memory controllers with 4 32-bit channels each for
DDR5. FSP has 16 positions to store SPD data, some of which are only
used with LPDDR4/LPDDR5.
To try to make things less confusing, FSP abstracts the DDR5 channels
so that the configuration works like on DDR4. This is done by copying
each DIMM's SPD data to the other half-channel. Thus, fix the wrapper
parameters for DDR5 accordingly.
BUG=None
TEST=Build fatcat and verify there are no errors
Change-Id: I10226a2e04905040523d95ba8f5bc56f45606fe6
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91201
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
The Root complex always resides at 0:0.0 and is always enabled.
Add a static device in DSDT that can be extended later on.
Change-Id: I1d45f7cd732c41343ac154c313a7ca368b0ea2b3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91183
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add SMM_TSEG_SIZE for Apollo Lake and Gemini Lake, set to same value as
used by other Intel SoCs. This is required since commit c078552e71
("soc/intel: Replace sa_get_tseg_size() with CONFIG_SMM_TSEG_SIZE")
removed the use of sa_get_tseg_size() without verifying that all SoCs
actually set the Kconfig being used to replace it.
TEST=build google/reef and verify CONFIG_SMM_TSEG_SIZE set in .config.
Change-Id: Iaac2eaddc6ef3ccfa299b8b10103d26d08881370
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Add support to invoke LPASS Initialization. Implement
voting-based enablement for the core HM GDSC and AON CC PLL
instead of direct control.
BUG=b:480195888
Test=1. Create an image.serial.bin and ensure it boots on X1P42100.
2. Verified LP0 BCM vote using serial logs.
Serial Log:
[DEBUG] BCM: Found address 0x00050048 for resource LP0
[INFO ] BCM: Successfully voted for LP0 (addr=0x00050048, val=0x60004001)
3. Verified if the clocks are enabled by taking clock dump. Clock
enablement is verified by dumping the 31st bit of the corresponding
clock’s CBCR register. A value of 0 in bit 31 indicates that the clock
is ON. The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
4. Able to boot X1P42100 w/o any adsp failed to bootup error.
Change-Id: I51ca2b7a5da8b35d0d8dd803000f1db28441c136
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Select SOC_AMD_SUPPORTS_WARM_RESET on faegon only.
Glinda doesn't currently support warm resets.
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Change-Id: Ic7a011827d16685bb3f2a13a576b7832a4929119
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Currently FSP modifies the AOAC bits of the FCH devices and
thus needs the current status passed via fch_rt_device_enable_map.
By default fch_rt_device_enable_map is 0, effectly disabling all FCH
devices, including the debug UART. This causes a hang at boot.
Fill fch_rt_device_enable_map in SoC code.
TEST=Can boot on amd/birman_plus again.
Change-Id: I00ef35ea6fe11939c4154940fef8cb902955fe27
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The existing logic prioritized the check for ENV_ROMSTAGE_OR_BEFORE
over the HAVE_EARLY_POWEROFF_SUPPORT configuration. This meant that
platforms with early poweroff support might still fall through to the
incorrect path depending on the boot phase.
Refactor the logic to:
1. Prioritize CONFIG(HAVE_EARLY_POWEROFF_SUPPORT) as the primary
mechanism for poweroff.
2. If early support is not available, check the environment stage:
- Perform standard pmc_control_poweroff() if after romstage.
- Halt with an emergency message if attempted too early in the
boot process without platform support.
This structure ensures that platform-specific early poweroff routines
are always preferred when configured.
TEST=Able to verify the AC host event is not getting cleared after
power-off.
Change-Id: Ieec8bcae5e1002d264db59cafe9236aaef6576e0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Add the same wakeup method that Meteor Lake uses to Panther Lake.
TEST=Able to build and boot google/moonstone where able to wake
the device using differnt USB devices like USB FP, KB and Mouse.
Change-Id: Id680b443791c3dbc502d1b6776fd0fa03bd80691
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Remove the sa_get_tseg_size() function and replace all its usage with
CONFIG_SMM_TSEG_SIZE configuration option. The TSEG size is now
obtained directly from the configuration instead of being calculated
dynamically. The existing calculation assumes GSM and TSEG regions are
contiguous, but there is no guarantee this is always true depending on
how FSP operates. This could lead to incorrect size calculations.
Using CONFIG_SMM_TSEG_SIZE is more reliable as this value is provided
to the FSP during initialization.
This change:
- Removes sa_get_tseg_size() function declaration and implementation
- Updates smm_region() to use CONFIG_SMM_TSEG_SIZE directly
- Updates Alder Lake, Meteor Lake, and Panther Lake system agent code
to use CONFIG_SMM_TSEG_SIZE instead of sa_get_tseg_size()
Before (sa_get_tseg_size):
[SPEW ] TsegBase = 0x78000000
[SPEW ] GsmBase = 0x7BC00000
[DEBUG] sa_get_tseg_size:0x3c00000
[DEBUG] New SMBASE=0x7b5ec000 IEDBASE=0x7b800000
[DEBUG] Writing SMRR. base = 0x78000006, mask=0xfc400c00
System hangs during SMM relocation
After (CONFIG_SMM_TSEG_SIZE):
[SPEW ] TsegBase = 0x78000000
[SPEW ] GsmBase = 0x7BC00000
[DEBUG] CONFIG_SMM_TSEG_SIZE:0x2000000
[DEBUG] New SMBASE=0x799ec000 IEDBASE=0x79c00000
[DEBUG] Writing SMRR. base = 0x78000006, mask=0xfe000c00
[DEBUG] Relocation complete.
System boots successfully
BUG=none
Change-Id: Ie2a1f3dd68941924e056a12f01857c1182b69198
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91063
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit increases the default pre-allocated IGD stolen memory size
from 64MB to 128MB in FSP-M parameters. This ensures sufficient memory
is allocated for higher resolution displays and graphics-intensive
early-boot tasks on Panther Lake platforms.
BUG=b:481209815
TEST=Able to build and boot google/ruby.
Change-Id: Idd3f1bcb9cbb27adc18a31c0dd5952e901ecf5eb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91126
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the Integrated Graphics Device (IGD) stolen memory size enum
values to align with the Panther Lake Reference Code. This change
introduces the 96MB definition and corrects the value for 128MB.
Modified values:
- IGD_SM_96MB: Added as 0x03
- IGD_SM_128MB: Updated from 0x03 to 0x04
Change-Id: Id7a547e8a530294a76f201e87865e8508ff67a92
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91140
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch provides support for board-specific fine-tuning of PCIe root
ports.
The following parameters can be adjusted.
PchPcieHsioTxGen1DownscaleAmp:
- Adjust the transmitter driver strength and its output swing for Gen 1
PCIe devices
PchPcieHsioTxGen2DownscaleAmp:
- Adjust the transmitter driver strength and its output swing for Gen 2
PCIe devices
PchPcieHsioTxGen3DownscaleAmp:
- Adjust the transmitter driver strength and its output swing for Gen 3
PCIe devices
PchPcieHsioTxGen1DeEmph:
- Adjust or fine-tune the amount for PCIe Gen 1 devices by which the
output is de-emphasized for -3.5dB mode
PchPcieHsioTxGen2DeEmph3p5:
- Adjust or fine-tune the amount for PCIe Gen 2 devices by which the
output is de-emphasized for -3.5dB mode
PchPcieHsioTxGen2DeEmph6p0:
- Adjust or fine-tune the amount for PCIe Gen 2 devices by which the
output is de-emphasized for -6.0dB mode
Change-Id: I7b51de2b7f75e15d902e471a19b8b29166ddfb48
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The existing PLATFORM_LOW_BATTERY_SHUTDOWN_DELAY_SEC was strictly
tied to the low-battery indicator logic. This change renames and
generalizes the configuration to PLATFORM_POST_RENDER_DELAY_SEC.
By moving this out of the low-battery specific conditional block in
Kconfig, the delay can now be utilized more broadly. While it still
ensures the low-battery warning remains visible before power-off, it
can now also be used to ensure display synchronization or user
notifications are visible before passing control to the OS in normal
boot flows.
Updated Intel common reset logic to utilize the renamed config.
BUG=b:473480933
TEST=Verified that low-battery shutdown still respects the 5-second
default delay on target hardware.
Change-Id: I0277ea278fb299499f6eab2be983761a8f6ba536
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91104
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Align the MPinit code with other Intel CPU drivers and move the
microcode update on the BSP to pre_mp_init(). This also ensures that
the microcode is located in CBFS before the MTRRs are set up using
x86_setup_mtrrs_with_detect() which removes caching the SPI flash
MMIO area.
No functional change, thus untested.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I47573dde5d471c9654ea9f14bd24b2a7087dd6df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add all known PCI bridge devices to the DSDT. This allows to reference
the devices from DSDT, allowing to add more SoC DSDT code and it allows
mainboard developers to add board specific ACPI code for devices behind
PCIe bridges (like NVMe D3cold).
Currently this is only possible using SSDT generators. The SSDT ACPI
generation is also broken, since the mainboard SSDT is run before SoC
SSDT, causing the interpreter to complain about missing devices.
TEST=Still boots on amd/birman_plus. No ACPI errors seen in dmesg.
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Change-Id: I9d6f84b97fa943bb531d6b7b3f16c0422cd7901f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89456
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Load microcode from CBFS before setting up MTRRs using
x86_setup_mtrrs_with_detect(), since it will remove caching the
SPI flash MMIO area and thus slow down CBFS accesses.
TEST=Booted on AMD/crater with CBFS_VERIFICATION enabled. The system
boots 6msec faster than before.
Change-Id: I3fafb98c1348daa549448707db88954316a12ff2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
JSL was missing an entry for the IGD, preventing the use of
DRIVERS_GFX_GENERIC since the call to acpi_device_scope() for it
returned null. Add the missing IGD entry, consistent with other
modern Intel SoCs.
TEST=build/boot google/magolor with chip drivers/gfx/generic entry
and verify SSDT entry correctly created.
Change-Id: Idf1d8992b45c60f68fd2b156c6e7cae816df84b4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Simplify Wildcat Lake SKU configuration by consolidating multiple
SKU variants into a single WCL_SKU_1 configuration. All WCL device
IDs (WCL_ID_2 through WCL_ID_5) now map to WCL_SKU_1 instead of
having separate SKU definitions.
Additionally, update GT domain VR controller settings for WCL_SKU_1:
- Set IccMax to 36A (144 in register units) for GT domain
BUG=b:467349691
TEST=Build ocelot and verify system boots with consolidated WCL SKU
configuration. Confirm GT VR IccMax is set to 36A in coreboot logs.
Change-Id: I6466c150bcd712430cf2595db5be13039688fecb
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90803
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: P, Usha <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Increase the maximum root port count for Panther Lake (PTL) to 12.
While the actual number of active ports may vary depending on the
specific SKU and strapping, setting this constant to 12 is safe
and systematically handled by the existing SoC logic.
Systematic Bounds: The common PCIe root port driver (pcie_rp.c)
and PTL-specific FSP parameter logic utilize ptl_rp_groups and
PCI configuration space accesses to determine the actual hardware
limits at runtime.
Safe Ceiling: CONFIG_MAX_ROOT_PORTS serves as a compile-time upper
bound for array allocations and iteration loops. Setting this to
12 accommodates the maximum possible PTL configuration without
over-allocating resources.
Consistency: This aligns the configuration with the hardware's
maximum capability, allowing the silicon initialization code to
dynamically "fill in" the details for lower-port SKUs without
requiring further Kconfig changes.
BUG=None
TEST=Able to build boards that use different PTL SKUs.
Change-Id: Icb8f2c075aa56531e311d1ce718953fe3366a5e2
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91078
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 261274992d.
Reason for revert: Panther Lake U/H Processor EDS vol 1/2 says PTL-U/H
12Xe has 12 PCIe RPs where else PTL-H 4Xe has 10 PCIe RPs.
This change has limit the capability for devices that is build with
PTL-U/H 12Xe hence, we are seeing below errors
```
[ERROR] pcie_rp_update_devicetree: Error: Group exceeds
CONFIG_MAX_ROOT_PORTS.
```
As a result PCIe Gen 5 devices (SSD) unable to init and enabled during
boot.
Change-Id: I0443554ef8f619c485f16edc576794f9cf2e85ea
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91075
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
configure_tdp() selects the power limit table based on the
SA PCI device ID and the CPU's nominal TDP.
Add a 45W entry for PCI_DID_INTEL_ARL_H_ID_1 (e.g. Intel
285H) so power limits are programmed instead of being
skipped.
Change-Id: Ia90633b43b78bc616ff0b750ed3ef44333019957
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91056
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As discussed under CB:88768, building for PantherLake targets fails due
to odd race-condition:
```
src/include/stdint.h:66:9: error: "INT32_MAX" redefined [-Werror]
66 | #define INT32_MAX ((int32_t)0x7FFFFFFF)
| ^~~~~~~~~
[...]
129 | #define INT32_MAX (0x7FFFFFFF)
| ^~~~~~~~~
cc1: all warnings being treated as errors
make: *** Waiting for unfinished jobs....
```
Board maintainers shouldn't need to include the FSP API header in their
ports, adding this header globally to meminit.h resolves the
race-condition and allows the build to finish.
Change-Id: Id7656d476ca6db78ea74629ef37a20323362997a
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91023
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Make PCIe ASPM/L1SS CFR options depend on PCIe Clock Power Management
so the setup UI can hide them when CLK PM is disabled.
Change-Id: I7dc778bc2d6fb15d6062a4ab855bc8b700c22fad
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The GPIO pad community definition for Skylake does not set the
pad_cfg_lock_offset member, leading to an "offset not defined for pad"
error when trying to lock a pad config in gpio_non_smm_lock_pad(). This
must be set to the offset of the first Pad Configuration Lock register
within each GPIO communities register blocks which can be found in the
GPIO sections of the processor I/O and PCH-H datasheets.
References:
Skylake-U/Y: Intel 332691
Sunrise Point-H: Intel 332996
Kaby Lake-U/Y: Intel 334659
Union Point-H: Intel 335193
Change-Id: I2991a7cbfb333d9fdda008cbb4cbc272aa508ef0
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
According to EDS #872188, PTL-H484 has 8 more PCIe
lanes than PTL-H404 and 12Xe SKUs.
I believe there's been a mixup during bringup, as PCIe ACPI tables are
"gated" for an SKU with more PCIe 5.0 lanes.
To be exact, in a file: "src/soc/intel/pantherlake/acpi/ptl_pcie.asl"
we can notice PCIe 5.0 RootPorts depending on SOC_INTEL_PANTHERLAKE_H.
Google/Fatcat boards seem to be using PANTHERLAKE_U_H instead.
TEST: Build/boot intel/pantherlake_crb. Make sure Linux doesn't report
PCIe routing errors.
Change-Id: I1d136cf1959a3851d0ac37b256fd4df28a8d30df
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
protection
Add support for runtime control of BIOS lock
(BOOTMEDIA_SMM_BWP) via the CFR option API. This allows
users to enable/disable BIOS write protection in SMM
through the setup menu when explicitly enabled.
The implementation adds a new "bios_lock" CFR option that:
- Controls SMM BIOS write protection at runtime
- Sets EISS (Enable InSMM.STS) when enabled
- Enables SPI/LPC write protection in SMM
- Prevents unauthorised BIOS modifications outside SMM
Security model:
- Runtime control is opt-in via
BOOTMEDIA_SMM_BWP_RUNTIME_OPTION config
- When disabled, the option is suppressed in CFR
(not exposed in UI)
- Compile-time CONFIG(BOOTMEDIA_SMM_BWP) serves as the
default/fallback
- Protects against unauthorised EFI variable
modifications, bypassing BIOS lock when the runtime
option is not enabled
The option is integrated into Intel's common lockdown
code and SMI handlers, replacing compile-time-only
checks with conditional runtime lookups where
BOOTMEDIA_SMM_BWP_RUNTIME_OPTION is enabled.
Change-Id: Ie3b63462501e0d204c33dc3f8a006b73da0899d3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89919
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the ModPHY settings are also available on other Intel platforms,
these parameters should be moved to common code.
Change-Id: Ic2666c7bbd576681dea7f360c396c068b42306e2
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90943
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In the first boot after coreboot is flashed, ABL FW performs
memory training and passes APOB data to coreboot. coreboot
writes APOB data in SPI flash along with hash of the APOB data.
If APOB signature is not written in CMOS, Memory context is
not restored by ABL in subsequent boot and full training is
initiated which increases boot time.coreboot keeps writing the
APOB data to flash in every boot due to hash mismatch of APOB
data which inturn increases boot time.This change fixes the
issue of ABL FW not doing Memory Context restore due to missing
CMOS signature.On some older platforms FSP writes this signature
unconditionally and hence this coreboot patch doesnt impact
the older platforms.
TEST= Validated on crater platform. APOB write is not initiated
by coreboot on every boot. APOB write to flash happens only once
after the coreboot flash.
Change-Id: Id799d0d2ed9f54e29db7681509f3d66c1638b6ac
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90947
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix regression introduced by commit d18cc50e6a ("soc/intel/xeon_sp:
Use common smm_relocate").
The MSR SMM_FEATURE_CONTROL_MSR is only implemented on client SoCs.
Starting from Haswell server onwards the "SMM feature control" on
server platforms resides on the UBOX in PCI space.
Parallel SMM relocation was never supported on server platforms, thus
disable parallel SMM relocation for now and thus fix booting on all
Xeon-SP platforms. Added a FIXME to possibly implement this feature
in the future.
TEST=Can boot on OCP/tiogapass again.
Change-Id: I7b4fbe633046acbf9f921cca722ff343a64962cd
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
The generic Intel SMM S5 entry path disables all GPEs before asserting
SLP_EN, which clears OS-armed wake enables (e.g. LAN_WAKE) and prevents
Wake-on-LAN from S5.
Add a mainboard override hook, mainboard_smi_sleep_finalize(), called
after the S5 teardown but before SLP_EN is asserted, allowing boards to
restore required wake sources.
Change-Id: I9e97308ed94961fc4c08a10714b1b53f198bb593
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add USB port aliases to chipset_glk.cb and chipset_apl.cb to enable
boards to use device ref syntax for USB devices. Port counts match
hardware specs: GLK has 9 USB2/7 USB3 ports, APL has 8 USB2/7 USB3
ports.
Select 'DRIVERS_USB_ACPI' so that the required USB ACPI drivers are
built and linked for all boards.
Change-Id: Ibc7dd2cbfda8c8eb42b243ea7adcdb6d1fdea98b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Select SOC_INTEL_COMMON_BLOCK_ASPM and use the SoC common code for
programming PCIe root port power management. This adds programming of
PCIe RP clock PM and port speed, as well as allows for user override
via setup options for all fields. Remove the now-unused static methods
get_l1_substate_control() and get_aspm_control().
Additionally, check the port enable status before declaring the root
port config struct, to be consistent with ADL and MTL.
Change-Id: Ic30d714e609612ea46d34252c7c1d799652a9c2b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90879
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move SDXC device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from sd.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
This standardizes the approach across Intel SoCs and makes the
SDXC controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.
Change-Id: Ifee16988d0e5625a7b3c2be51ab70d2c8471747a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Move CNVI WiFi device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them.
Remove corresponding DIDs from cnvi.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
Remove the static declaration from cnvi_wifi_ops so the symbol is
exported and visible outside of cnvi.c.
This standardizes the approach across Intel SoCs and makes the
CNVI WiFi controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.
Change-Id: I82a2b20a8b967d1a3d5a80ae477def260c366be7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90922
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move XDCI device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from xdci.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
This standardizes the approach across Intel SoCs and makes the
XDCI controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.
Change-Id: Ie8f8b5a952d072ecd1721bc8537734e85769b09d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Move XHCI device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from xhci.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
This standardizes the approach across Intel SoCs and makes the
XHCI controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.
Change-Id: I4a0551a0fc5a233153c62d5bb7b0b2f3596a81ac
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Move HDA device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from hda.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
Add 'Select SOC_INTEL_COMMON_BLOCK_HDA` to Apollolake/Geminilake
so those platforms can make use of the common driver. Since no
APL/GLK boards currently select `SOC_INTEL_COMMON_BLOCK_HDA_VERB`
the addition is a no-op.
This standardizes the approach across Intel SoCs and makes the
HDA controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common HDA driver code.
Change-Id: I0b3af4c2a441d4897341ee6c2cc5d75d70a6ebc4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90919
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move SMBUS device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from smbus.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
This standardizes the approach across Intel SoCs and makes the
SMBUS controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.
Change-Id: I1c742836d923eb8f521bdbd7fa8260c82c1156ac
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Move GSPI/SPI device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from spi.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
This standardizes the approach across Intel SoCs and makes the
GSPI/SPI controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.
Change-Id: Ia379cff36a5b277d89cad757edc094a5d786a51b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90917
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move UART device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from uart.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
This standardizes the approach across Intel SoCs and makes the
UART controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.
Change-Id: Id26dad7997d64bcaad53fa39be23e52cb47dcc1d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90916
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move SATA device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from sata.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
Add `select SOC_INTEL_COMMON_BLOCK_SATA` to Apollolake SoC so that
the common block code is included, which it was not previously, even
though the APL/GLK PCI DIDs were included in the list. The net
effect is that the `SATA` ACPI device is now added to SSDT for
APL/GLK boards when they have SATA enabled.
This standardizes the approach across Intel SoCs and makes the
SATA controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.
Change-Id: I4c296a88c4da5f91d1039877ec858857496527f0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Move I2C device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from i2c.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
This standardizes the approach across Intel SoCs and makes the
I2C controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common I2C driver code.
Change-Id: Ib68dd19c7c94d4cb6b41a1caf092b77f463c1c74
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90906
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Move PCIe root port operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from pcie.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files. Some of these
will be removed/cleaned up in subsequent patches.
This standardizes the approach across Intel SoCs and makes the
PCIe root port configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common PCIe driver code.
Change-Id: I8586b6efb8dbe164bc2a1d68b7131ffa22b00001
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Similar to other Intel SoCs, create a chipset.cb for Jasperlake
giving alias names to all known PCI devices. Taken from comments in
existing JSL board devicetrees, cross-referenced against the publicly
available JSL EDS.
At the same time, remove the usb2_lte device aliases in the BOTEN and
DRAWCIA dedede variants, and replace their references with the new
usb2_port4 alias, since we can only have a single alias per device.
TEST=build boten and drawcia dedede variants
Change-Id: I32552dbe0ab5305ea44b5e89432603884cf6589f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Commit ad6e3c847f ("tree: Drop Intel Ice Lake support") removed most
of the Ice Lake PCI IDs, but missed the ones with the ICP prefix
(Ice Point? Ice Lake Point?). Remove all PCI_DID_INTEL_ICP* defines
and references in common block drivers.
Change-Id: I9d33c69d174130aa781a00441fca367e0a67bcb4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90904
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Add Turin OpenSIL driver and submodule pointing to turin_poc branch
of github.com/openSIL/openSIL repository.
Change-Id: Idd6d4e78a055926061de330da620c943b42a50a7
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
