soc/amd/common/block/acp/acp: Drop acpi_device_write_pci_dev

Move the ACP ACPI device called ACPD from SSDT to DSDT so that a SoC
or a mainboard DSDT can extend the ACP configuration.
Therefore, drop acpi_device_write_pci_dev() in SSDT. Introduce a STAT
variable in ASL, which defaults to 3 (present, enabled, hidden, not ok)
when the device is set to "off" in the devicetree.cb, since the PCI
device is not actual disabled by FSP. When not disabled in devicetree.cb,
STAT will be overriden in SSDT with the actual device status. The STAT
variable is returned by _STA method.

The ACP child devices where seen on Phoenix and KrackenPoint and not
seen on Rembrandt, Cezanne or Mendocino.
Assume older platforms do not have ACP child devices in ACPI.

TEST=Booted on AMD birman_plus (glinda) and verified ACP is working.
TEST=Set ACP device to off and verified it's marked hidden on Windows 11
     Device Manager.

Change-Id: I31c3f01f83f27d0121f9e003e60a7f12d49427f6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/soc/amd/cezanne/acpi/acp.asl

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* ACP Audio Configuration */
+Scope (\_SB.PCI0.GP41) {
+	Device (ACPD) {
+		/* Device addressing for ACP (Audio Coprocessor) */
+		Name (_ADR, 0x05)  /* Device 0, Function 5 */
+
+		Name (STAT, 0x3) /* Decoding Resources, Hide from UI */
+		Method (_STA, 0x0, NotSerialized)
+		{
+			Return (STAT)
+		}
+	}
+}

src/soc/amd/cezanne/acpi/soc.asl

@@ -24,6 +24,8 @@ Scope(\_SB) {
 
 		#include "pci.asl"
 	} /* End PCI0 scope */
+
+	#include "acp.asl"
 } /* End \_SB scope */
 
 #include <soc/amd/common/acpi/alib.asl>

src/soc/amd/common/block/acp/acp.c

@@ -22,23 +22,30 @@ static const char *acp_acpi_name(const struct device *dev)
 static void acp_fill_wov_method(const struct device *dev)
 {
 	const struct soc_amd_common_config *cfg = soc_get_common_config();
-	const char *scope = acpi_device_path(dev);
 
-	if (!cfg->acp_config.dmic_present || !scope)
+	if (!cfg->acp_config.dmic_present)
 		return;
 
 	/* For ACP DMIC hardware runtime detection on the platform, _WOV method is populated. */
-	acpigen_write_scope(scope); /* Scope */
 	acpigen_write_method("_WOV", 0);
 	acpigen_write_return_integer(1);
 	acpigen_write_method_end();
-	acpigen_write_scope_end();
 }
 
 static void acp_fill_ssdt(const struct device *dev)
 {
-	acpi_device_write_pci_dev(dev);
+	const char *scope = acpi_device_path(dev);
+	assert(scope);
+	if (!scope)
+		return;
+
+	acpigen_write_scope(scope);
+
+	acpigen_write_store_int_to_namestr(acpi_device_status(dev), "STAT");
 	acp_fill_wov_method(dev);
+
+	acpigen_pop_len(); /* Scope */
+
 	if (CONFIG(SOC_AMD_COMMON_BLOCK_ACP_SOC_SPECIFIC_SSDT_ENTRY))
 		acp_soc_write_ssdt_entry(dev);
 }

src/soc/amd/glinda/acpi/acp.asl

@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* ACP Audio Configuration */
+Scope (\_SB.PCI0.GP41) {
+	Device (ACPD) {
+		/* Device addressing for ACP (Audio Coprocessor) */
+		Name (_ADR, 0x05)  /* Device 0, Function 5 */
+
+		Name (STAT, 0x3) /* Decoding Resources, Hide from UI */
+		Method (_STA, 0x0, NotSerialized)
+		{
+			Return (STAT)
+		}
+
+		/* Child Devices - Audio endpoints */
+		Device (HDA0)   /* HDA0 - HD Audio */
+		{
+			Name (_ADR, 0x01)
+		}
+
+		Device (PDMC)   /* PDM Controller */
+		{
+			Name (_ADR, 0x02)
+		}
+
+		Device (I2SC)   /* I2S Controller */
+		{
+			Name (_ADR, 0x03)
+		}
+
+		Device (BTSC)   /* BT Sideband Controller */
+		{
+			Name (_ADR, 0x04)
+		}
+
+		Device (SDWC)   /* SoundWire Controller */
+		{
+			Name (_ADR, 0x05)
+		}
+
+		Device(SDWS)	/* SoundWire Streaming */
+		{
+			Name (_ADR, 0x06)
+		}
+
+		Device(USBS)	/* USB Sideband */
+		{
+			Name (_ADR, 0x07)
+		}
+	}
+}

src/soc/amd/glinda/acpi/soc.asl

@@ -26,6 +26,9 @@ Scope(\_SB) {
 
 		#include "pci.asl"
 	} /* End PCI0 scope */
+
+	#include "acp.asl"
+
 } /* End \_SB scope */
 
 #include <soc/amd/common/acpi/alib.asl>

src/soc/amd/mendocino/acpi/acp.asl

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* ACP Audio Configuration */
+Scope (\_SB.PCI0.GP41) {
+	Device (ACPD) {
+		/* Device addressing for ACP (Audio Coprocessor) */
+		Name (_ADR, 0x05)  /* Device 0, Function 5 */
+
+		Name (STAT, 0x3) /* Decoding Resources, Hide from UI */
+		Method (_STA, 0x0, NotSerialized)
+		{
+			Return (STAT)
+		}
+	}
+}

src/soc/amd/mendocino/acpi/soc.asl

@@ -26,6 +26,9 @@ Scope(\_SB) {
 
 		#include "pci.asl"
 	} /* End PCI0 scope */
+
+	#include "acp.asl"
+
 } /* End \_SB scope */
 
 #include <soc/amd/common/acpi/alib.asl>

src/soc/amd/phoenix/acpi/acp.asl

@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* ACP Audio Configuration */
+Scope (\_SB.PCI0.GP41) {
+	Device (ACPD) {
+		/* Device addressing for ACP (Audio Coprocessor) */
+		Name (_ADR, 0x05)  /* Device 0, Function 5 */
+
+		Name (STAT, 0x3) /* Decoding Resources, Hide from UI */
+		Method (_STA, 0x0, NotSerialized)
+		{
+			Return (STAT)
+		}
+
+		/* Child Devices - Audio endpoints */
+		Device (HDA0)   /* HDA0 - HD Audio */
+		{
+			Name (_ADR, 0x01)
+		}
+
+		Device (PDMC)   /* PDM Controller */
+		{
+			Name (_ADR, 0x02)
+		}
+
+		Device (I2SC)   /* I2S Controller */
+		{
+			Name (_ADR, 0x03)
+		}
+
+		Device (BTSC)   /* BT Sideband Controller */
+		{
+			Name (_ADR, 0x04)
+		}
+
+		Device (SDWC)   /* SoundWire Controller */
+		{
+			Name (_ADR, 0x05)
+		}
+
+		Device (SDWS)	/* SoundWire Streaming */
+		{
+			Name (_ADR, 0x06)
+		}
+
+		Device (USBS)	/* USB Sideband */
+		{
+			Name (_ADR, 0x07)
+		}
+	}
+}

src/soc/amd/phoenix/acpi/soc.asl

@@ -26,6 +26,9 @@ Scope(\_SB) {
 
 		#include "pci.asl"
 	} /* End PCI0 scope */
+
+	#include "acp.asl"
+
 } /* End \_SB scope */
 
 #include <soc/amd/common/acpi/alib.asl>

src/soc/amd/picasso/acpi/acp.asl

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* ACP Audio Configuration */
+Scope (\_SB.PCI0.GP41) {
+	Device (ACPD) {
+		/* Device addressing for ACP (Audio Coprocessor) */
+		Name (_ADR, 0x05)  /* Device 0, Function 5 */
+
+		Name (STAT, 0x3) /* Decoding Resources, Hide from UI */
+		Method (_STA, 0x0, NotSerialized)
+		{
+			Return (STAT)
+		}
+	}
+}

src/soc/amd/picasso/acpi/soc.asl

@@ -38,6 +38,8 @@ Scope(\_SB) { /* Start \_SB scope */
 	/* Describe the MMIO devices in the FCH */
 	#include "mmio.asl"
 
+	#include "acp.asl"
+
 	/* Add GPIO library */
 	#include <soc/amd/common/acpi/gpio_bank_lib.asl>