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soc/intel/skylake: Set pad_cfg_lock_offset in skl_gpio_communities

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The GPIO pad community definition for Skylake does not set the
pad_cfg_lock_offset member, leading to an "offset not defined for pad"
error when trying to lock a pad config in gpio_non_smm_lock_pad(). This
must be set to the offset of the first Pad Configuration Lock register
within each GPIO communities register blocks which can be found in the
GPIO sections of the processor I/O and PCH-H datasheets.

References:
Skylake-U/Y: Intel 332691
Sunrise Point-H: Intel 332996
Kaby Lake-U/Y: Intel 334659
Union Point-H: Intel 335193

Change-Id: I2991a7cbfb333d9fdda008cbb4cbc272aa508ef0
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Nicholas Chin 2026-01-24 19:20:21 -07:00 • committed by Matt DeVillier
commit e2d3d9758d
2 changed files with 17 additions and 0 deletions
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4
src/soc/intel/skylake/gpio.c
View file

@ -57,6 +57,7 @@ static const struct pad_community skl_gpio_communities[] = {
.last_pad = GPP_B23,
.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET_COM0,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
@ -81,6 +82,7 @@ static const struct pad_community skl_gpio_communities[] = {
#endif
.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET_COM1,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
@ -106,6 +108,7 @@ static const struct pad_community skl_gpio_communities[] = {
#endif
.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET_COM3,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,
@ -126,6 +129,7 @@ static const struct pad_community skl_gpio_communities[] = {
.last_pad = GPD11,
.num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET_COM2,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_int_sts_reg_0 = GPI_INT_STS_0,
.gpi_int_en_reg_0 = GPI_INT_EN_0,

13
src/soc/intel/skylake/include/soc/gpio_defs.h
View file

@ -209,6 +209,19 @@
#define GPIO_DRIVER_IRQ_ROUTE_IRQ14 0
#define GPIO_DRIVER_IRQ_ROUTE_IRQ15 8
#define HOSTSW_OWN_REG_0 0xd0
#if CONFIG(SKYLAKE_SOC_PCH_H)
#define PAD_CFG_LOCK_OFFSET_COM0 0xa0
#define PAD_CFG_LOCK_OFFSET_COM1 0x90
#define PAD_CFG_LOCK_OFFSET_COM2 0x90
#define PAD_CFG_LOCK_OFFSET_COM3 0x90
#else
#define PAD_CFG_LOCK_OFFSET_COM0 0xa0
#define PAD_CFG_LOCK_OFFSET_COM1 0xa0
#define PAD_CFG_LOCK_OFFSET_COM2 0xa0
#define PAD_CFG_LOCK_OFFSET_COM3 0xa0
#endif /* CONFIG(SKYLAKE_SOC_PCH_H) */
#define PAD_CFG_BASE 0x400
#define GPI_INT_STS_0 0x100
#define GPI_INT_EN_0 0x120