soc/intel/pantherlake: Set CONFIG_MAX_ROOT_PORTS to 12

Increase the maximum root port count for Panther Lake (PTL) to 12.
While the actual number of active ports may vary depending on the
specific SKU and strapping, setting this constant to 12 is safe
and systematically handled by the existing SoC logic.

Systematic Bounds: The common PCIe root port driver (pcie_rp.c)
and PTL-specific FSP parameter logic utilize ptl_rp_groups and
PCI configuration space accesses to determine the actual hardware
limits at runtime.

Safe Ceiling: CONFIG_MAX_ROOT_PORTS serves as a compile-time upper
bound for array allocations and iteration loops. Setting this to
12 accommodates the maximum possible PTL configuration without
over-allocating resources.

Consistency: This aligns the configuration with the hardware's
maximum capability, allowing the silicon initialization code to
dynamically "fill in" the details for lower-port SKUs without
requiring further Kconfig changes.

BUG=None
TEST=Able to build boards that use different PTL SKUs.

Change-Id: Icb8f2c075aa56531e311d1ce718953fe3366a5e2
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91078
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/pantherlake/Kconfig

@@ -253,7 +253,6 @@ config MAX_TBT_ROOT_PORTS
 config MAX_ROOT_PORTS
 	int
 	default 6 if SOC_INTEL_WILDCATLAKE
-	default 10 if SOC_INTEL_PANTHERLAKE_H
 	default 12
 
 config MAX_PCIE_CLOCK_SRC