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soc/intel/jasperlake: Move PCIe ModPHY parameter to common pcie_rp.h

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Since the ModPHY settings are also available on other Intel platforms,
these parameters should be moved to common code.

Change-Id: Ic2666c7bbd576681dea7f360c396c068b42306e2
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90943
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mario Scheithauer 2026-01-27 10:04:08 +01:00 • committed by Matt DeVillier
commit 9ae5af54cc
3 changed files with 19 additions and 26 deletions
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20
src/soc/intel/common/block/include/intelblocks/pcie_rp.h
View file

@ -3,7 +3,7 @@
#ifndef SOC_INTEL_COMMON_BLOCK_PCIE_RP_H
#define SOC_INTEL_COMMON_BLOCK_PCIE_RP_H
#include <stdint.h>
#include <types.h>
/*
* In schematic PCIe root port numbers are 1-based, but FSP use 0-based indexes for
@ -85,6 +85,24 @@ struct pcie_rp_config {
enum PCIE_SPEED_control pcie_rp_pcie_speed;
};
struct pcie_modphy_config {
/* TX Output Downscale Amplitude Adjustment */
bool tx_gen1_downscale_amp_override;
uint8_t tx_gen1_downscale_amp;
/* TX Output Downscale Amplitude Adjustment */
bool tx_gen2_downscale_amp_override;
uint8_t tx_gen2_downscale_amp;
/* TX Output Downscale Amplitude Adjustment */
bool tx_gen3_downscale_amp_override;
uint8_t tx_gen3_downscale_amp;
/* TX Output -3.5dB Mode De-Emphasis Adjustment Setting */
uint8_t tx_gen1_de_emph;
/* TX Output -3.5dB Mode De-Emphasis Adjustment Setting */
uint8_t tx_gen2_de_emph_3p5;
/* TX Output -6.0dB Mode De-Emphasis Adjustment Setting */
uint8_t tx_gen2_de_emph_6p0;
};
/*
* The PCIe Root Ports usually come in groups of up to 8 PCI-device
* functions.

1
src/soc/intel/jasperlake/chip.h
View file

@ -15,7 +15,6 @@
#include <soc/gpe.h>
#include <soc/pch.h>
#include <soc/pci_devs.h>
#include <soc/pcie_modphy.h>
#include <soc/pmc.h>
#include <soc/serialio.h>
#include <soc/usb.h>

24
src/soc/intel/jasperlake/include/soc/pcie_modphy.h
View file

@ -1,24 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _SOC_JASPERLAKE_PCIE_MODPHY_H_
#define _SOC_JASPERLAKE_PCIE_MODPHY_H_
struct pcie_modphy_config {
/* TX Output Downscale Amplitude Adjustment */
bool tx_gen1_downscale_amp_override;
uint8_t tx_gen1_downscale_amp;
/* TX Output Downscale Amplitude Adjustment */
bool tx_gen2_downscale_amp_override;
uint8_t tx_gen2_downscale_amp;
/* TX Output Downscale Amplitude Adjustment */
bool tx_gen3_downscale_amp_override;
uint8_t tx_gen3_downscale_amp;
/* TX Output -3.5dB Mode De-Emphasis Adjustment Setting */
uint8_t tx_gen1_de_emph;
/* TX Output -3.5dB Mode De-Emphasis Adjustment Setting */
uint8_t tx_gen2_de_emph_3p5;
/* TX Output -6.0dB Mode De-Emphasis Adjustment Setting */
uint8_t tx_gen2_de_emph_6p0;
};
#endif