soc/amd/cezanne: Move SSDT code into DSDT
Now that the ACP device is always present in DSDT move the MSG0 method and helper functions into DSDT. This allows to clean the common ACP code and reduces differences in the runtime code pathes. The newly introduced DSDT is also verified at compile time. Change-Id: Ifc55278aa66abcb54691017738cc843e3088d8e8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91159 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Rudolph
Matt DeVillier
parent
8c56a9c53e
commit
4e61dd36e4
6 changed files with 79 additions and 235 deletions
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@ -26,7 +26,6 @@ config SOC_AMD_CEZANNE_BASE
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select RTC
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select SOC_AMD_COMMON
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select SOC_AMD_COMMON_BLOCK_ACP_GEN1
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select SOC_AMD_COMMON_BLOCK_ACP_SOC_SPECIFIC_SSDT_ENTRY
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select SOC_AMD_COMMON_BLOCK_ACPI
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select SOC_AMD_COMMON_BLOCK_ACPIMMIO
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select SOC_AMD_COMMON_BLOCK_ACPIMMIO_PM_IO_ACCESS
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@ -92,226 +92,3 @@ const acpi_cstate_t *get_cstate_config_data(size_t *size)
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*size = ARRAY_SIZE(cstate_cfg_table);
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return cstate_cfg_table;
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}
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static void acp_soc_write_smn_access_methods(void)
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{
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acpigen_write_method_serialized("SMNR", 1);
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acpigen_write_store_op_to_namestr(ARG0_OP, "\\_SB.PCI0.GNB.SMNA");
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acpigen_write_return_namestr("\\_SB.PCI0.GNB.SMND");
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acpigen_write_method_end();
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acpigen_write_method_serialized("SMNW", 2);
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acpigen_write_store_op_to_namestr(ARG0_OP, "\\_SB.PCI0.GNB.SMNA");
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acpigen_write_store_op_to_namestr(ARG1_OP, "\\_SB.PCI0.GNB.SMND");
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acpigen_write_method_end();
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}
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/* write value of ACPI variable into SMN register */
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static void acp_soc_write_smn_register_write(uint8_t op, uint32_t smn_address)
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{
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acpigen_emit_namestring("^SMNW");
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acpigen_write_integer(smn_address);
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acpigen_emit_byte(op);
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}
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/* read SMN register and store value into ACPI variable */
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static void acp_soc_write_smn_register_read(uint32_t smn_address, uint8_t op)
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{
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acpigen_write_store();
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acpigen_emit_namestring("^SMNR");
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acpigen_write_integer(smn_address);
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acpigen_emit_byte(op);
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}
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static void acp_soc_write_mailbox_access(void)
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{
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acp_soc_write_smn_register_write(ARG0_OP, 0x00058A74);
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acp_soc_write_smn_register_write(ARG1_OP, 0x00058A54);
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acp_soc_write_smn_register_write(ARG2_OP, 0x00058A14);
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acp_soc_write_smn_register_read(0x00058A74, LOCAL0_OP);
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/* While (LEqual (Local0, 0)) */
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acpigen_emit_byte(WHILE_OP);
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acpigen_write_len_f();
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acpigen_emit_byte(LEQUAL_OP);
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acpigen_emit_byte(LOCAL0_OP);
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acpigen_emit_byte(ZERO_OP);
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acp_soc_write_smn_register_read(0x00058A74, LOCAL0_OP);
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acpigen_pop_len(); /* While */
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acp_soc_write_smn_register_read(0x00058A54, LOCAL1_OP);
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acpigen_write_return_op(LOCAL1_OP);
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}
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static void acp_soc_write_psp_mbox_buffer_field(void)
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{
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acpigen_write_name("MBOX");
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acpigen_write_byte_buffer(NULL, 4);
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acpigen_write_create_buffer_word_field("MBOX", 0, "STAT");
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acpigen_write_create_buffer_byte_field("MBOX", 2, "CMDI");
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acpigen_write_create_buffer_bit_field("MBOX", 31, "REDY");
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}
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static void acp_soc_write_psp_read_mbox_from_hw(void)
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{
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acp_soc_write_smn_register_read(0x03810570, LOCAL0_OP);
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acpigen_write_store_op_to_namestr(LOCAL0_OP, "MBOX");
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}
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static void acp_soc_write_psp_write_mbox_to_hw(void)
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{
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acpigen_write_store_namestr_to_op("MBOX", LOCAL0_OP);
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acp_soc_write_smn_register_write(LOCAL0_OP, 0x03810570);
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}
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static void acp_soc_write_psp_mailbox_access(void)
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{
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acp_soc_write_psp_mbox_buffer_field();
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acp_soc_write_psp_read_mbox_from_hw();
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/* While (LOr (LNotEqual (REDY, 0x1), LNotEqual (CMDI, 0x00))) */
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acpigen_emit_byte(WHILE_OP);
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acpigen_write_len_f();
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acpigen_emit_byte(LOR_OP);
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acpigen_emit_byte(LNOT_OP);
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acpigen_emit_byte(LEQUAL_OP);
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acpigen_emit_namestring("REDY");
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acpigen_write_integer(1);
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acpigen_emit_byte(LNOT_OP);
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acpigen_emit_byte(LEQUAL_OP);
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acpigen_emit_namestring("CMDI");
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acpigen_write_integer(0);
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acp_soc_write_psp_read_mbox_from_hw();
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acpigen_pop_len(); /* While */
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acpigen_write_store_int_to_op(0, LOCAL0_OP);
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acpigen_write_store_op_to_namestr(LOCAL0_OP, "MBOX");
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acpigen_write_store_int_to_namestr(0x33, "CMDI");
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acp_soc_write_psp_write_mbox_to_hw();
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acpigen_write_sleep(1);
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acp_soc_write_psp_read_mbox_from_hw();
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/* While (LNotEqual (CMDI, 0x00)) */
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acpigen_emit_byte(WHILE_OP);
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acpigen_write_len_f();
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acpigen_emit_byte(LNOT_OP);
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acpigen_emit_byte(LEQUAL_OP);
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acpigen_emit_namestring("CMDI");
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acpigen_write_integer(0);
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acp_soc_write_psp_read_mbox_from_hw();
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acpigen_pop_len(); /* While */
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acpigen_write_return_op(LOCAL0_OP);
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}
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static void acp_soc_write_msg0_method(void)
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{
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acpigen_write_method_serialized("MSG0", 3);
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/* If (ARG2 != 0x9) */
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acpigen_write_if_lnotequal_op_int(ARG2_OP, 0x9);
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acp_soc_write_mailbox_access();
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acpigen_write_else();
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acp_soc_write_psp_mailbox_access();
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acpigen_write_if_end();
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acpigen_write_method_end(); /* MSG0 */
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}
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void acp_soc_write_ssdt_entry(const struct device *dev)
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{
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/*
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* SMN and mailbox interface using the SMN OperationRegion on the host bridge
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*
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* Provide both SMN read/write methods for direct SMN register access and the MSG0
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* method which is used by some ACP drivers to access two different mailbox interfaces
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* in the hardware. One mailbox interface is used to configure the ACP's clock source,
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* the other one is used to notify the PSP that the DSP firmware has been loaded, so
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* that the PSP can validate the firmware and set the qualifier bit to enable running
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* it.
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*
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* Scope (\_SB.PCI0.GP41.ACPD)
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* {
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* Method (SMNR, 1, Serialized)
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* {
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* Store (Arg0, \_SB.PCI0.GNB.SMNA)
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* Return (\_SB.PCI0.GNB.SMND)
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* }
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*
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* Method (SMNW, 2, Serialized)
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* {
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* Store (Arg0, \_SB.PCI0.GNB.SMNA)
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* Store (Arg1, \_SB.PCI0.GNB.SMND)
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* }
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*
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* Method (MSG0, 3, Serialized)
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* {
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* If (LNotEqual (Arg2, 0x09))
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* {
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* ^SMNW (0x00058A74, Arg0)
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* ^SMNW (0x00058A54, Arg1)
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* ^SMNW (0x00058A14, Arg2)
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* Store (^SMNR (0x00058A74), Local0)
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* While (LEqual (Local0, Zero))
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* {
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* Store (^SMNR (0x00058A74), Local0)
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* }
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* Store (^SMNR (0x00058A54), Local1)
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* Return (Local1)
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* }
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* Else
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* {
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* Name (MBOX, Buffer (0x04){})
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* CreateWordField (MBOX, Zero, STAT)
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* CreateByteField (MBOX, 0x02, CMDI)
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* CreateBitField (MBOX, 0x1F, REDY)
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* Store (^SMNR (0x03810570), Local0)
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* Store (Local0, MBOX)
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* While (LOr (LNotEqual (REDY, One), LNotEqual (CMDI, Zero)))
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* {
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* Store (^SMNR (0x03810570), Local0)
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* Store (Local0, MBOX)
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* }
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* Store (Zero, Local0)
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* Store (Local0, MBOX)
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* Store (0x33, CMDI)
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* Store (MBOX, Local0)
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* ^SMNW (0x03810570, Local0)
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* Sleep (One)
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* Store (^SMNR (0x03810570), Local0)
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* Store (Local0, MBOX)
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* While (LNotEqual (CMDI, Zero))
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* {
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* Store (^SMNR (0x03810570), Local0)
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* Store (Local0, MBOX)
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* }
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* Return (Local0)
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* }
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* }
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* }
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*/
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acpigen_write_scope(acpi_device_path(dev));
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acp_soc_write_smn_access_methods();
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acp_soc_write_msg0_method();
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acpigen_write_scope_end();
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}
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@ -10,5 +10,84 @@ Scope (\_SB.PCI0.GP41) {
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{
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Return (STAT)
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}
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External (\_SB.PCI0.GNB.SMNA, FieldUnitObj)
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External (\_SB.PCI0.GNB.SMND, FieldUnitObj)
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/* Read SMN register and store value into ACPI variable */
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Method (SMNR, 1, Serialized)
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{
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\_SB.PCI0.GNB.SMNA = Arg0
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Return (\_SB.PCI0.GNB.SMND)
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}
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/* Write value of ACPI variable into SMN register */
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Method (SMNW, 2, Serialized)
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{
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\_SB.PCI0.GNB.SMNA = Arg0
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\_SB.PCI0.GNB.SMND = Arg1
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}
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/*
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* SMN and mailbox interface using the SMN OperationRegion on the host bridge
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*
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* Provide both SMN read/write methods for direct SMN register access and the MSG0
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* method which is used by some ACP drivers to access two different mailbox interfaces
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* in the hardware. One mailbox interface is used to configure the ACP's clock source,
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* the other one is used to notify the PSP that the DSP firmware has been loaded, so
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* that the PSP can validate the firmware and set the qualifier bit to enable running
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* it.
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*/
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Method (MSG0, 3, Serialized)
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{
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If (Arg2 != 0x09)
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{
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/* mailbox access */
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^SMNW (0x00058A74, Arg0)
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^SMNW (0x00058A54, Arg1)
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^SMNW (0x00058A14, Arg2)
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Local0 = ^SMNR (0x00058A74)
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While (Local0 == 0)
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{
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Local0 = ^SMNR (0x00058A74)
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}
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Local1 = ^SMNR (0x00058A54)
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Return (Local1)
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}
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Else
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{
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/* PSP mailbox access */
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Name (MBOX, Buffer (0x04) {
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0x20, 0x57, 0x91, 0x7B
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})
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CreateWordField (MBOX, Zero, STAT)
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CreateByteField (MBOX, 0x02, CMDI)
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CreateBitField (MBOX, 0x1F, REDY)
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Local0 = ^SMNR (0x03810570)
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MBOX = Local0
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While (((REDY != 1) || (CMDI != 0)))
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{
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Local0 = ^SMNR (0x03810570)
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MBOX = Local0
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}
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Local0 = Zero
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MBOX = Local0
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CMDI = 0x33
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Local0 = MBOX
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^SMNW (0x03810570, Local0)
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Sleep (1)
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Local0 = ^SMNR (0x03810570)
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MBOX = Local0
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While (CMDI != 0)
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{
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Local0 = ^SMNR (0x03810570)
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MBOX = Local0
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}
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Return (Local0)
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}
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}
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}
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}
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@ -11,9 +11,3 @@ config SOC_AMD_COMMON_BLOCK_ACP_GEN2
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help
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Select this option to perform Audio Co-Processor(ACP) configuration.
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Used by the ACP in AMD mendocino (family 17h) and possibly newer CPUs.
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config SOC_AMD_COMMON_BLOCK_ACP_SOC_SPECIFIC_SSDT_ENTRY
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bool
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help
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Select this option to call into the SoC code when generating the SSDT
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entry for the Audio Co-Processor (ACP).
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@ -45,9 +45,6 @@ static void acp_fill_ssdt(const struct device *dev)
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acp_fill_wov_method(dev);
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acpigen_pop_len(); /* Scope */
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if (CONFIG(SOC_AMD_COMMON_BLOCK_ACP_SOC_SPECIFIC_SSDT_ENTRY))
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acp_soc_write_ssdt_entry(dev);
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}
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struct device_operations amd_acp_ops = {
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@ -45,6 +45,4 @@ struct acp_config {
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bool dmic_present;
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};
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void acp_soc_write_ssdt_entry(const struct device *dev);
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#endif /* AMD_COMMON_ACP_H */
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