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soc/intel/ehl: Add PCIe High Speed I/O ModPHY support

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This patch provides support for board-specific fine-tuning of PCIe root
ports.

The following parameters can be adjusted.

PchPcieHsioTxGen1DownscaleAmp:
- Adjust the transmitter driver strength and its output swing for Gen 1
  PCIe devices
PchPcieHsioTxGen2DownscaleAmp:
- Adjust the transmitter driver strength and its output swing for Gen 2
  PCIe devices
PchPcieHsioTxGen3DownscaleAmp:
- Adjust the transmitter driver strength and its output swing for Gen 3
  PCIe devices
PchPcieHsioTxGen1DeEmph:
- Adjust or fine-tune the amount for PCIe Gen 1 devices by which the
  output is de-emphasized for -3.5dB mode
PchPcieHsioTxGen2DeEmph3p5:
- Adjust or fine-tune the amount for PCIe Gen 2 devices by which the
  output is de-emphasized for -3.5dB mode
PchPcieHsioTxGen2DeEmph6p0:
- Adjust or fine-tune the amount for PCIe Gen 2 devices by which the
  output is de-emphasized for -6.0dB mode

Change-Id: I7b51de2b7f75e15d902e471a19b8b29166ddfb48
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Mario Scheithauer 2026-01-27 10:20:16 +01:00 • committed by Werner Zeh
commit c463b7761e
2 changed files with 39 additions and 0 deletions
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3
src/soc/intel/elkhartlake/chip.h
View file

@ -238,6 +238,9 @@ struct soc_intel_elkhartlake_config {
/* PCIe RP L1 substate */
enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
/* PCIe ModPhy related */
struct pcie_modphy_config pcie_mp_cfg[CONFIG_MAX_ROOT_PORTS];
/* PCIe root port maximum payload size, default is set to 128 bytes. */
enum {
RpMaxPayload_128,

36
src/soc/intel/elkhartlake/romstage/fsp_params.c
View file

@ -22,6 +22,8 @@ enum {
static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
const struct soc_intel_elkhartlake_config *config)
{
size_t i;
/*
* If IGD is enabled, set IGD stolen size to 60MB.
* Otherwise, skip IGD init in FSP.
@ -33,6 +35,40 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->SaGv = config->SaGv;
m_cfg->RMT = config->RMT;
/* PCIe ModPhy configuration */
for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
if (config->pcie_mp_cfg[i].tx_gen1_downscale_amp_override) {
m_cfg->PchPcieHsioTxGen1DownscaleAmpEnable[i] = 1;
m_cfg->PchPcieHsioTxGen1DownscaleAmp[i] =
config->pcie_mp_cfg[i].tx_gen1_downscale_amp;
}
if (config->pcie_mp_cfg[i].tx_gen2_downscale_amp_override) {
m_cfg->PchPcieHsioTxGen2DownscaleAmpEnable[i] = 1;
m_cfg->PchPcieHsioTxGen2DownscaleAmp[i] =
config->pcie_mp_cfg[i].tx_gen2_downscale_amp;
}
if (config->pcie_mp_cfg[i].tx_gen3_downscale_amp_override) {
m_cfg->PchPcieHsioTxGen3DownscaleAmpEnable[i] = 1;
m_cfg->PchPcieHsioTxGen3DownscaleAmp[i] =
config->pcie_mp_cfg[i].tx_gen3_downscale_amp;
}
if (config->pcie_mp_cfg[i].tx_gen1_de_emph) {
m_cfg->PchPcieHsioTxGen1DeEmphEnable[i] = 1;
m_cfg->PchPcieHsioTxGen1DeEmph[i] =
config->pcie_mp_cfg[i].tx_gen1_de_emph;
}
if (config->pcie_mp_cfg[i].tx_gen2_de_emph_3p5) {
m_cfg->PchPcieHsioTxGen2DeEmph3p5Enable[i] = 1;
m_cfg->PchPcieHsioTxGen2DeEmph3p5[i] =
config->pcie_mp_cfg[i].tx_gen2_de_emph_3p5;
}
if (config->pcie_mp_cfg[i].tx_gen2_de_emph_6p0) {
m_cfg->PchPcieHsioTxGen2DeEmph6p0Enable[i] = 1;
m_cfg->PchPcieHsioTxGen2DeEmph6p0[i] =
config->pcie_mp_cfg[i].tx_gen2_de_emph_6p0;
}
}
m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(pch_rp_groups);
FSP_ARRAY_LOAD(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage);