soc/intel/common/block/cpu/smmrelocate: Fix regression
Fix regression introduced by commit d18cc50e6a ("soc/intel/xeon_sp:
Use common smm_relocate").
The MSR SMM_FEATURE_CONTROL_MSR is only implemented on client SoCs.
Starting from Haswell server onwards the "SMM feature control" on
server platforms resides on the UBOX in PCI space.
Parallel SMM relocation was never supported on server platforms, thus
disable parallel SMM relocation for now and thus fix booting on all
Xeon-SP platforms. Added a FIXME to possibly implement this feature
in the future.
TEST=Can boot on OCP/tiogapass again.
Change-Id: I7b4fbe633046acbf9f921cca722ff343a64962cd
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This commit is contained in:
parent
56403e52a1
commit
8ec0dc7356
2 changed files with 9 additions and 8 deletions
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@ -78,6 +78,15 @@ static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params)
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{
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msr_t smm_mca_cap;
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/*
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* FIXME: On Xeon-SP the MSR SMM_FEATURE_CONTROL_MSR is not implemented.
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* SMM feature control resides on the UBOX PCI device.
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* FIXME: Need to enable save state in MSRs on all sockets, however BSP
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* runs on a single socket only.
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*/
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if (CONFIG(XEON_SP_COMMON_BASE) || CONFIG(SOC_INTEL_SNOWRIDGE))
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return 0;
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smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR);
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if (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK) {
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msr_t smm_feature_control;
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@ -5,14 +5,6 @@
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#include <intelblocks/msr.h>
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/**
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* @brief Force serialized SMM relocation by hardcoding `SMM_CPU_SVRSTR` feature as not supported.
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*/
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#ifdef SMM_CPU_SVRSTR_MASK
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#undef SMM_CPU_SVRSTR_MASK
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#endif
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#define SMM_CPU_SVRSTR_MASK 0
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#define MSR_BIOS_DONE 0x151
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#define ENABLE_IA_UNTRUSTED BIT(0)
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