Michał Żygowski 4d1d27fcf3 vendorcode/amd/opensil: Add Turin OpenSIL ... Add Turin OpenSIL driver and submodule pointing to turin_poc branch of github.com/openSIL/openSIL repository. Change-Id: Idd6d4e78a055926061de330da620c943b42a50a7 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>		2026-01-28 13:32:33 +00:00
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amd	vendorcode/amd/opensil: Add Turin OpenSIL	2026-01-28 13:32:33 +00:00
cavium
example/min86
ibm/power9	soc/power9/rom_media.c: find CBFS in PNOR	2025-08-28 20:14:01 +00:00
intel	soc/intel/{mtl,ptl}/fsp_params: Program PcieRpDetectTimeoutMs	2026-01-25 19:06:40 +00:00
mediatek	soc/mediatek/common: Combine dsi_cmdq_size register writes	2026-01-25 19:06:22 +00:00
nvidia	treewide: Move mipi_panel_parse_commands() to commonlib	2026-01-14 09:38:36 +00:00
qualcomm	soc/qualcomm/x1p42100: Relocate CBMEM top to PIL region base	2026-01-28 05:51:14 +00:00
rockchip	treewide: Move mipi_panel_parse_commands() to commonlib	2026-01-14 09:38:36 +00:00
samsung	samsung/exynos5250: Replace 'unsigned long int' by 'unsigned long'	2025-01-15 08:32:16 +00:00
sifive	tree: Remove unused <assert.h>	2024-11-19 00:40:04 +00:00
ti
ucb/riscv	soc/riscv/ucb: Switch to FDT parsing to get memory size	2025-02-26 17:11:09 +00:00
xilinx	soc/xilinx/zynq7000: Initial Xilinx Zynq 7000 SoC bringup	2025-01-23 00:41:01 +00:00