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soc/intel/apollolake: Align MPinit code

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Align the MPinit code with other Intel CPU drivers and move the
microcode update on the BSP to pre_mp_init(). This also ensures that
the microcode is located in CBFS before the MTRRs are set up using
x86_setup_mtrrs_with_detect() which removes caching the SPI flash
MMIO area.

No functional change, thus untested.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I47573dde5d471c9654ea9f14bd24b2a7087dd6df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Patrick Rudolph 2026-01-26 07:36:20 +01:00
commit 4772d019f3
1 changed files with 5 additions and 3 deletions
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8
src/soc/intel/apollolake/cpu.c
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@ -162,6 +162,11 @@ static void pre_mp_init(void)
fsps_load();
return;
}
/* Make sure BSP is using the microcode from cbfs */
const struct microcode *microcode_patch = intel_microcode_find();
intel_microcode_load_unlocked(microcode_patch);
x86_setup_mtrrs_with_detect();
x86_mtrr_check();
}
@ -192,9 +197,6 @@ void get_microcode_info(const void **microcode, int *parallel)
{
*microcode = intel_microcode_find();
*parallel = 1;
/* Make sure BSP is using the microcode from cbfs */
intel_microcode_load_unlocked(*microcode);
}
#endif