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soc/qualcomm/x1p42100: Add support to invoke LPASS Init

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Add support to invoke LPASS Initialization. Implement
voting-based enablement for the core HM GDSC and AON CC PLL
instead of direct control.

BUG=b:480195888
Test=1. Create an image.serial.bin and ensure it boots on X1P42100.
2. Verified LP0 BCM vote using serial logs.
Serial Log:
[DEBUG]  BCM: Found address 0x00050048 for resource LP0
[INFO ]  BCM: Successfully voted for LP0 (addr=0x00050048, val=0x60004001)
3. Verified if the clocks are enabled by taking clock dump. Clock
enablement is verified by dumping the 31st bit of the corresponding
clock’s CBCR register. A value of 0 in bit 31 indicates that the clock
is ON. The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
4. Able to boot X1P42100 w/o any adsp failed to bootup error.

Change-Id: I51ca2b7a5da8b35d0d8dd803000f1db28441c136
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Swathi Tamilselvan 2026-02-06 18:59:27 +05:30 • committed by Subrata Banik
commit 74df39f65e
4 changed files with 23 additions and 12 deletions
Download patch file Download diff file Expand all files Collapse all files

10
src/soc/qualcomm/x1p42100/include/soc/clock.h
View file

@ -66,6 +66,7 @@ enum clk_ctl_lpass_aon_cc_pll_user_ctl_x1p42100 {
AON_CC_PLL_PLLOUT_ODD_SHFT_X1P42100 = 2,
AON_CC_PLL_POST_DIV_EVEN_SHFT_X1P42100 = 10,
AON_CC_PLL_POST_DIV_ODD_SHFT_X1P42100 = 14,
AON_CC_PLL_ENABLE_VOTE_RUN = 25
};
enum clk_pll_src {
@ -280,16 +281,19 @@ struct x1p42100_lpass_aon_cc {
u32 va_mem0_cbcr;
u8 _res1[0x2c];
u32 lpass_audio_hm_gdscr;
u8 _res2[0x8F78];
u8 _res2[0x2f6c];
u32 lpass_hm_collapse_vote_for_q6;
u8 _res3[0x6008];
u32 va_2x_cbcr;
u8 _res3[0x4];
u8 _res4[0x4];
u32 va_cbcr;
u8 _res4[0xffc];
u8 _res5[0xffc];
u32 tx_mclk_cbcr;
};
check_member(x1p42100_lpass_aon_cc, va_mem0_cbcr, 0x9060);
check_member(x1p42100_lpass_aon_cc, lpass_audio_hm_gdscr, 0x9090);
check_member(x1p42100_lpass_aon_cc, lpass_hm_collapse_vote_for_q6, 0xc000);
check_member(x1p42100_lpass_aon_cc, va_2x_cbcr, 0x1200C);
check_member(x1p42100_lpass_aon_cc, va_cbcr, 0x12014);
check_member(x1p42100_lpass_aon_cc, tx_mclk_cbcr, 0x13014);

6
src/soc/qualcomm/x1p42100/include/soc/lpass.h
View file

@ -8,7 +8,8 @@
/* LPASS AON CC PLL Settings */
#define HAL_CLK_LPASS_AON_CC_PLL_L_VALUE 0x00000020
#define HAL_CLK_LPASS_AON_CC_PLL_ALPHA_VALUE 0x00000000
#define HAL_CLK_LPASS_AON_CC_PLL_CAL_L_VALUE 0x00000044
#define HAL_CLK_LPASS_AON_CC_PLL_RING_CAL_L_VALUE (0x44 << 16)
#define HAL_CLK_LPASS_AON_CC_PLL_PROC_CAL_L_VALUE (0x44 << 24)
#define HAL_CLK_LPASS_AON_CC_PLL_CONFIG_CTL 0x20485699
#define HAL_CLK_LPASS_AON_CC_PLL_CONFIG_CTL_U 0x00182261
#define HAL_CLK_LPASS_AON_CC_PLL_CONFIG_CTL_U1 0x82AA299C
@ -23,5 +24,8 @@
#define HW_CTL BIT(1)
#define GDSC_ENABLE_BIT 0
#define LPASS_CORE_HM_VOTE_POWER_ON 0x0
#define GDSC_PWR_ON BIT(31)
#define BCM_LP0_VOTE_VALUE 0x60004001
#endif /* _SOC_QUALCOMM_X1P42100_LPASS_H_ */

17
src/soc/qualcomm/x1p42100/lpass.c
View file

@ -13,13 +13,14 @@ static enum cb_err lpass_aon_cc_pll_enable(void)
pll_cfg.reg_mode = &lpass_aon_cc_pll->pll_mode;
pll_cfg.reg_l = &lpass_aon_cc_pll->pll_l_val;
pll_cfg.l_val = HAL_CLK_LPASS_AON_CC_PLL_L_VALUE;
pll_cfg.l_val = HAL_CLK_LPASS_AON_CC_PLL_L_VALUE |
HAL_CLK_LPASS_AON_CC_PLL_PROC_CAL_L_VALUE |
HAL_CLK_LPASS_AON_CC_PLL_RING_CAL_L_VALUE;
pll_cfg.reg_alpha = &lpass_aon_cc_pll->pll_alpha_val;
pll_cfg.alpha_val = HAL_CLK_LPASS_AON_CC_PLL_ALPHA_VALUE;
pll_cfg.reg_cal_l = &lpass_aon_cc_pll->pll_l_val;
pll_cfg.cal_l_val = HAL_CLK_LPASS_AON_CC_PLL_CAL_L_VALUE;
pll_cfg.reg_config_ctl = &lpass_aon_cc_pll->pll_config_ctl;
pll_cfg.config_ctl_val = HAL_CLK_LPASS_AON_CC_PLL_CONFIG_CTL;
@ -45,10 +46,8 @@ static enum cb_err lpass_aon_cc_pll_enable(void)
write32(&lpass_aon_cc_pll->pll_test_ctl_u1, HAL_CLK_LPASS_AON_CC_PLL_TEST_CTL_U1);
write32(&lpass_aon_cc_pll->pll_test_ctl_u2, HAL_CLK_LPASS_AON_CC_PLL_TEST_CTL_U2);
if (lucidole_pll_enable(&pll_cfg) != CB_SUCCESS) {
printk(BIOS_ERR, "LPASS: AON CC PLL enable failed\n");
return CB_ERR;
}
setbits32(&lpass_aon_cc_pll->pll_user_ctl, BIT(AON_CC_PLL_ENABLE_VOTE_RUN));
setbits32(&lpass_aon_cc_pll->pll_mode, BIT(PLL_RESET_SHFT));
setbits32(&lpass_aon_cc_pll->pll_user_ctl, (BIT(AON_CC_PLL_PLLOUT_EVEN_SHFT_X1P42100) |
BIT(AON_CC_PLL_PLLOUT_ODD_SHFT_X1P42100)));
@ -66,8 +65,10 @@ static enum cb_err lpass_setup_core_infrastructure(void)
setbits32(&lpass_core_gdsc->lpass_top_cc_lpass_core_sway_ahb_ls_cbcr, HW_CTL);
if (enable_and_poll_gdsc_status(&lpass_core_gdsc->core_hm_gdscr) != CB_SUCCESS) {
printk(BIOS_ERR, "LPASS: Failed to enable Core HM GDSC\n");
write32(&lpass_aon_cc->lpass_hm_collapse_vote_for_q6, LPASS_CORE_HM_VOTE_POWER_ON);
if (!wait_us(150000, !(read32(&lpass_core_gdsc->core_hm_gdscr) & GDSC_PWR_ON))) {
printk(BIOS_ERR, "LPASS: Core HM GDSC PWR_ON timeout after vote\n");
return CB_ERR;
}

2
src/soc/qualcomm/x1p42100/soc.c
View file

@ -5,6 +5,7 @@
#include <soc/mmu_common.h>
#include <soc/symbols_common.h>
#include <soc/pcie.h>
#include <soc/clock.h>
#include <soc/cpucp.h>
#include <program_loading.h>
@ -89,6 +90,7 @@ static void soc_init(struct device *dev)
{
cpucp_fw_load_reset();
qtee_fw_config_load();
lpass_init();
}
static struct device_operations soc_ops = {