Matt DeVillier e519cacd26 soc/intel: Use chipset.cb for GSPI device ops linking ... Move GSPI/SPI device operations linking from PCI Device ID matching to chipset.cb files for all Intel SoCs that have them, matching the approach used by Skylake. Remove corresponding DIDs from spi.c for these SoCs; keep DID matching only for SoCs without chipset.cb files. This standardizes the approach across Intel SoCs and makes the GSPI/SPI controller configuration explicit in devicetree, and prevents the endless proliferation of DIDs in the common driver code. Change-Id: Ia379cff36a5b277d89cad757edc094a5d786a51b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90917 Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2026-01-28 13:38:26 +00:00
..
amd	vendorcode/amd/opensil: Add Turin OpenSIL	2026-01-28 13:32:33 +00:00
cavium
example/min86
ibm/power9	soc/power9/rom_media.c: find CBFS in PNOR	2025-08-28 20:14:01 +00:00
intel	soc/intel: Use chipset.cb for GSPI device ops linking	2026-01-28 13:38:26 +00:00
mediatek	soc/mediatek/common: Combine dsi_cmdq_size register writes	2026-01-25 19:06:22 +00:00
nvidia	treewide: Move mipi_panel_parse_commands() to commonlib	2026-01-14 09:38:36 +00:00
qualcomm	soc/qualcomm/x1p42100: Relocate CBMEM top to PIL region base	2026-01-28 05:51:14 +00:00
rockchip	treewide: Move mipi_panel_parse_commands() to commonlib	2026-01-14 09:38:36 +00:00
samsung	samsung/exynos5250: Replace 'unsigned long int' by 'unsigned long'	2025-01-15 08:32:16 +00:00
sifive
ti
ucb/riscv	soc/riscv/ucb: Switch to FDT parsing to get memory size	2025-02-26 17:11:09 +00:00
xilinx	soc/xilinx/zynq7000: Initial Xilinx Zynq 7000 SoC bringup	2025-01-23 00:41:01 +00:00