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soc/amd/common/block/cpu/smm: Move microcode load

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Load microcode from CBFS before setting up MTRRs using
x86_setup_mtrrs_with_detect(), since it will remove caching the
SPI flash MMIO area and thus slow down CBFS accesses.

TEST=Booted on AMD/crater with CBFS_VERIFICATION enabled. The system
     boots 6msec faster than before.

Change-Id: I3fafb98c1348daa549448707db88954316a12ff2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Patrick Rudolph 2026-01-24 09:50:08 +01:00 • committed by Felix Held
commit aee21f53cc
1 changed files with 3 additions and 2 deletions
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5
src/soc/amd/common/block/cpu/smm/smm_relocate.c
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@ -17,10 +17,11 @@
/* AP MTRRs will be synced to the BSP in the SIPI vector so set them up before MP init. */
static void pre_mp_init(void)
{
x86_setup_mtrrs_with_detect();
x86_mtrr_check();
if (CONFIG(SOC_AMD_COMMON_BLOCK_UCODE))
amd_load_microcode_from_cbfs();
x86_setup_mtrrs_with_detect();
x86_mtrr_check();
}
static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,