soc/amd/common/block/apob: Fix APOB data hash mismatch issue

In the first boot after coreboot is flashed, ABL FW performs
memory training and passes APOB data to coreboot. coreboot
writes APOB data in SPI flash along with hash of the APOB data.
If APOB signature is not written in CMOS, Memory context is
not restored by ABL in subsequent boot and full training is
initiated which increases boot time.coreboot keeps writing the
APOB data to flash in every boot due to hash mismatch of APOB
data which inturn increases boot time.This change fixes the
issue of ABL FW not doing Memory Context restore due to missing
CMOS signature.On some older platforms FSP writes this signature
unconditionally and hence this coreboot patch doesnt impact
the older platforms.

TEST= Validated on crater platform. APOB write is not initiated
by coreboot on every boot. APOB write to flash happens only once
after the coreboot flash.

Change-Id: Id799d0d2ed9f54e29db7681509f3d66c1638b6ac
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90947
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/common/block/apob/apob_cache.c

@@ -17,6 +17,7 @@
 #include <thread.h>
 #include <timestamp.h>
 #include <types.h>
+#include <pc80/mc146818rtc.h>
 
 #define DEFAULT_MRC_CACHE	"RW_MRC_CACHE"
 #define DEFAULT_MRC_CACHE_SIZE	FMAP_SECTION_RW_MRC_CACHE_SIZE
@@ -272,6 +273,10 @@ static void soc_update_apob_cache(void *unused)
 	if (CONFIG(SOC_AMD_COMMON_BLOCK_APOB_HASH))
 		update_apob_nv_hash(ram_hash, &write_rdev);
 
+	// update the signature in CMOS to indicate APOB updated.
+	cmos_write(0x5A, 0x86);
+	cmos_write(0xA5, 0x87);
+
 	timestamp_add_now(TS_AMD_APOB_END);
 
 	printk(BIOS_INFO, "Updated APOB in flash\n");