Nicholas Chin e2d3d9758d soc/intel/skylake: Set pad_cfg_lock_offset in skl_gpio_communities ... The GPIO pad community definition for Skylake does not set the pad_cfg_lock_offset member, leading to an "offset not defined for pad" error when trying to lock a pad config in gpio_non_smm_lock_pad(). This must be set to the offset of the first Pad Configuration Lock register within each GPIO communities register blocks which can be found in the GPIO sections of the processor I/O and PCH-H datasheets. References: Skylake-U/Y: Intel 332691 Sunrise Point-H: Intel 332996 Kaby Lake-U/Y: Intel 334659 Union Point-H: Intel 335193 Change-Id: I2991a7cbfb333d9fdda008cbb4cbc272aa508ef0 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>		2026-01-30 21:15:19 +00:00
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amd	soc/amd/common/block/apob: Fix APOB data hash mismatch issue	2026-01-29 14:21:00 +00:00
cavium
example/min86
ibm/power9	soc/power9/rom_media.c: find CBFS in PNOR	2025-08-28 20:14:01 +00:00
intel	soc/intel/skylake: Set pad_cfg_lock_offset in skl_gpio_communities	2026-01-30 21:15:19 +00:00
mediatek	soc/mediatek/common: Combine dsi_cmdq_size register writes	2026-01-25 19:06:22 +00:00
nvidia	treewide: Move mipi_panel_parse_commands() to commonlib	2026-01-14 09:38:36 +00:00
qualcomm	soc/qualcomm/x1p42100: Relocate CBMEM top to PIL region base	2026-01-28 05:51:14 +00:00
rockchip	treewide: Move mipi_panel_parse_commands() to commonlib	2026-01-14 09:38:36 +00:00
samsung
sifive
ti
ucb/riscv	soc/riscv/ucb: Switch to FDT parsing to get memory size	2025-02-26 17:11:09 +00:00
xilinx