soc/amd/*/acpi: Define PCI bridges in DSDT

Add all known PCI bridge devices to the DSDT. This allows to reference
the devices from DSDT, allowing to add more SoC DSDT code and it allows
mainboard developers to add board specific ACPI code for devices behind
PCIe bridges (like NVMe D3cold).

Currently this is only possible using SSDT generators. The SSDT ACPI
generation is also broken, since the mainboard SSDT is run before SoC
SSDT, causing the interpreter to complain about missing devices.

TEST=Still boots on amd/birman_plus. No ACPI errors seen in dmesg.

Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Change-Id: I9d6f84b97fa943bb531d6b7b3f16c0422cd7901f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89456
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/cezanne/acpi/pci.asl

@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/amd/common/acpi/pci_template.asl>
+
+/*
+ * Keep name in sync with SSDT generator pcie_gpp_acpi_name()!
+ * Currently the name is hex representation of dev->path.pci.devfn.
+ */
+
+/* PCIe GPP */
+ACPI_PCI_DEV(GP09, 1, 1)
+ACPI_PCI_DEV(GP0A, 1, 2)
+ACPI_PCI_DEV(GP0B, 1, 3)
+
+/* PCIe GPP */
+ACPI_PCI_DEV(GP11, 2, 1)
+ACPI_PCI_DEV(GP12, 2, 2)
+ACPI_PCI_DEV(GP13, 2, 3)
+ACPI_PCI_DEV(GP14, 2, 4)
+ACPI_PCI_DEV(GP15, 2, 5)
+ACPI_PCI_DEV(GP16, 2, 6)
+ACPI_PCI_DEV(GP17, 2, 7)
+
+/* Internal GPP bridges */
+ACPI_PCI_DEV(GP41, 8, 1)
+ACPI_PCI_DEV(GP42, 8, 2)
+ACPI_PCI_DEV(GP43, 8, 3)

src/soc/amd/cezanne/acpi/soc.asl

@@ -21,6 +21,8 @@ Scope(\_SB) {
 
 	Scope(PCI0) {
 		#include <soc/amd/common/acpi/lpc.asl>
+
+		#include "pci.asl"
 	} /* End PCI0 scope */
 } /* End \_SB scope */
 

src/soc/amd/common/acpi/pci_template.asl

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * Template for fixed PCI devices on the SoC. SSDT will emit STAT=1 when enabled
+ * in hardware and devicetree.cb. Allows to write DSDT code for such devices or
+ * it's children. Possible use cases:
+ * - PowerResources for devices behind PCIe bridges (NVVMe D3cold)
+ * - _DSM for ACP
+ * - BOCO and BACO for GPU
+ */
+#ifdef ACPI_PCI_DEV
+ #undef ACPI_PCI_DEV
+#endif
+#define ACPI_PCI_DEV(name, dev, fun) \
+	Device(name) {					\
+		Name(_ADR, (dev << 16) + fun)		\
+		Name (STAT, 0x0)			\
+		Method (_STA, 0, NotSerialized)		\
+		{					\
+			Return (STAT)			\
+		}					\
+	}

src/soc/amd/common/block/pci/pcie_gpp.c

@@ -28,22 +28,16 @@ static const char *pcie_gpp_acpi_name(const struct device *dev)
 
 static void acpi_device_write_gpp_pci_dev(const struct device *dev)
 {
-	const char *scope = acpi_device_scope(dev);
-	const char *name = acpi_device_name(dev);
+	const char *path = acpi_device_path(dev);
 
 	assert(dev->path.type == DEVICE_PATH_PCI);
-	assert(name);
-	assert(scope);
+	assert(path);
 
-	acpigen_write_scope(scope);
-	acpigen_write_device(name);
-
-	acpigen_write_ADR_pci_device(dev);
-	acpigen_write_STA(acpi_device_status(dev));
+	acpigen_write_scope(path);
 
+	acpigen_write_store_int_to_namestr(acpi_device_status(dev), "STAT");
 	acpigen_write_pci_GNB_PRT(dev);
 
-	acpigen_pop_len(); /* Device */
 	acpigen_pop_len(); /* Scope */
 }
 

src/soc/amd/glinda/acpi/pci.asl

@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/amd/common/acpi/pci_template.asl>
+
+/*
+ * Keep name in sync with SSDT generator pcie_gpp_acpi_name()!
+ * Currently the name is hex representation of dev->path.pci.devfn.
+ */
+
+/* USB4.0 bridge */
+ACPI_PCI_DEV(GP09, 1, 1)
+ACPI_PCI_DEV(GP0A, 1, 2)
+ACPI_PCI_DEV(GP0B, 1, 3)
+
+/* PCIe GPP */
+ACPI_PCI_DEV(GP11, 2, 1)
+ACPI_PCI_DEV(GP12, 2, 2)
+ACPI_PCI_DEV(GP13, 2, 3)
+ACPI_PCI_DEV(GP14, 2, 4)
+ACPI_PCI_DEV(GP15, 2, 5)
+ACPI_PCI_DEV(GP16, 2, 6)
+
+/* PCIe GPP */
+ACPI_PCI_DEV(GP19, 3, 1)
+ACPI_PCI_DEV(GP1A, 3, 2)
+ACPI_PCI_DEV(GP1B, 3, 3)
+ACPI_PCI_DEV(GP1C, 3, 4)
+ACPI_PCI_DEV(GP1D, 3, 5)
+ACPI_PCI_DEV(GP1E, 3, 6)
+
+/* Internal GPP bridges */
+ACPI_PCI_DEV(GP41, 8, 1)
+ACPI_PCI_DEV(GP42, 8, 2)
+ACPI_PCI_DEV(GP43, 8, 3)

src/soc/amd/glinda/acpi/soc.asl

@@ -23,6 +23,8 @@ Scope(\_SB) {
 
 	Scope(PCI0) {
 		#include <soc/amd/common/acpi/lpc.asl>
+
+		#include "pci.asl"
 	} /* End PCI0 scope */
 } /* End \_SB scope */
 

src/soc/amd/mendocino/acpi/pci.asl

@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/amd/common/acpi/pci_template.asl>
+
+/*
+ * Keep name in sync with SSDT generator pcie_gpp_acpi_name()!
+ * Currently the name is hex representation of dev->path.pci.devfn.
+ */
+
+/* PCIe GPP */
+ACPI_PCI_DEV(GP11, 2, 1)
+ACPI_PCI_DEV(GP12, 2, 2)
+ACPI_PCI_DEV(GP13, 2, 3)
+ACPI_PCI_DEV(GP14, 2, 4)
+ACPI_PCI_DEV(GP15, 2, 5)
+ACPI_PCI_DEV(GP16, 2, 6)
+
+/* Internal GPP bridges */
+ACPI_PCI_DEV(GP41, 8, 1)
+ACPI_PCI_DEV(GP42, 8, 2)
+ACPI_PCI_DEV(GP43, 8, 3)

src/soc/amd/mendocino/acpi/soc.asl

@@ -23,6 +23,8 @@ Scope(\_SB) {
 
 	Scope(PCI0) {
 		#include <soc/amd/common/acpi/lpc.asl>
+
+		#include "pci.asl"
 	} /* End PCI0 scope */
 } /* End \_SB scope */
 

src/soc/amd/phoenix/acpi/pci.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/amd/common/acpi/pci_template.asl>
+
+/*
+ * Keep name in sync with SSDT generator pcie_gpp_acpi_name()!
+ * Currently the name is hex representation of dev->path.pci.devfn.
+ */
+
+/* PCIe GPP */
+ACPI_PCI_DEV(GP09, 1, 1)
+ACPI_PCI_DEV(GP0A, 1, 2)
+ACPI_PCI_DEV(GP0B, 1, 3)
+ACPI_PCI_DEV(GP0C, 1, 4)
+
+/* PCIe GPP */
+ACPI_PCI_DEV(GP11, 2, 1)
+ACPI_PCI_DEV(GP12, 2, 2)
+ACPI_PCI_DEV(GP13, 2, 3)
+ACPI_PCI_DEV(GP14, 2, 4)
+ACPI_PCI_DEV(GP15, 2, 5)
+ACPI_PCI_DEV(GP16, 2, 6)
+
+/* USB4.0 bridges */
+ACPI_PCI_DEV(GP19, 3, 1)
+ACPI_PCI_DEV(GP21, 4, 1)
+
+/* Internal GPP bridges */
+ACPI_PCI_DEV(GP41, 8, 1)
+ACPI_PCI_DEV(GP42, 8, 2)
+ACPI_PCI_DEV(GP43, 8, 3)

src/soc/amd/phoenix/acpi/soc.asl

@@ -23,6 +23,8 @@ Scope(\_SB) {
 
 	Scope(PCI0) {
 		#include <soc/amd/common/acpi/lpc.asl>
+
+		#include "pci.asl"
 	} /* End PCI0 scope */
 } /* End \_SB scope */
 

src/soc/amd/picasso/acpi/pci.asl

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/amd/common/acpi/pci_template.asl>
+
+/*
+ * Keep name in sync with SSDT generator pcie_gpp_acpi_name()!
+ * Currently the name is hex representation of dev->path.pci.devfn.
+ */
+
+/* PCIe GPP */
+ACPI_PCI_DEV(GP09, 1, 1)
+ACPI_PCI_DEV(GP0A, 1, 2)
+ACPI_PCI_DEV(GP0B, 1, 3)
+ACPI_PCI_DEV(GP0C, 1, 4)
+ACPI_PCI_DEV(GP0D, 1, 5)
+ACPI_PCI_DEV(GP0E, 1, 6)
+ACPI_PCI_DEV(GP0F, 1, 7)
+
+/* Internal GPP bridges */
+ACPI_PCI_DEV(GP41, 8, 1)
+ACPI_PCI_DEV(GP42, 8, 2)
+ACPI_PCI_DEV(GP43, 8, 3)

src/soc/amd/picasso/acpi/soc.asl

@@ -22,6 +22,7 @@ Scope(\_SB) { /* Start \_SB scope */
 	Scope(PCI0) {
 		/* Describe the AMD Northbridge */
 		#include "northbridge.asl"
+		#include "pci.asl"
 
 		/* Describe the AMD Fusion Controller Hub */
 		#include <soc/amd/common/acpi/lpc.asl>