Matt DeVillier 317d2e43e5 soc/intel/apollolake: Add USB port aliases to chipset.cb ... Add USB port aliases to chipset_glk.cb and chipset_apl.cb to enable boards to use device ref syntax for USB devices. Port counts match hardware specs: GLK has 9 USB2/7 USB3 ports, APL has 8 USB2/7 USB3 ports. Select 'DRIVERS_USB_ACPI' so that the required USB ACPI drivers are built and linked for all boards. Change-Id: Ibc7dd2cbfda8c8eb42b243ea7adcdb6d1fdea98b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Eric Lai <ericllai@google.com>		2026-01-29 08:58:56 +00:00
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amd	vendorcode/amd/opensil: Add Turin OpenSIL	2026-01-28 13:32:33 +00:00
cavium
example/min86
ibm/power9	soc/power9/rom_media.c: find CBFS in PNOR	2025-08-28 20:14:01 +00:00
intel	soc/intel/apollolake: Add USB port aliases to chipset.cb	2026-01-29 08:58:56 +00:00
mediatek	soc/mediatek/common: Combine dsi_cmdq_size register writes	2026-01-25 19:06:22 +00:00
nvidia	treewide: Move mipi_panel_parse_commands() to commonlib	2026-01-14 09:38:36 +00:00
qualcomm	soc/qualcomm/x1p42100: Relocate CBMEM top to PIL region base	2026-01-28 05:51:14 +00:00
rockchip	treewide: Move mipi_panel_parse_commands() to commonlib	2026-01-14 09:38:36 +00:00
samsung	samsung/exynos5250: Replace 'unsigned long int' by 'unsigned long'	2025-01-15 08:32:16 +00:00
sifive
ti
ucb/riscv	soc/riscv/ucb: Switch to FDT parsing to get memory size	2025-02-26 17:11:09 +00:00
xilinx	soc/xilinx/zynq7000: Initial Xilinx Zynq 7000 SoC bringup	2025-01-23 00:41:01 +00:00