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soc/intel/pantherlake: Fix DDR5 channel mapping

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This patch applies commit 0e7cf3d81d ("soc/intel/alderlake: Fix DDR5
channel mapping") to PantherLake.

DDR5 memory modules have two separate 32-bit channels (40-bit on ECC
memory modules), and the SPD info refers to one channel: the primary
bus width is 32 (or 40) bits and the "DIMM size" is halved. On Panther
Lake, there are 2 memory controllers with 4 32-bit channels each for
DDR5. FSP has 16 positions to store SPD data, some of which are only
used with LPDDR4/LPDDR5.

To try to make things less confusing, FSP abstracts the DDR5 channels
so that the configuration works like on DDR4. This is done by copying
each DIMM's SPD data to the other half-channel. Thus, fix the wrapper
parameters for DDR5 accordingly.

BUG=None
TEST=Build fatcat and verify there are no errors

Change-Id: I10226a2e04905040523d95ba8f5bc56f45606fe6
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91201
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit is contained in:
Avi Uday 2026-02-13 18:31:39 +05:30 • committed by Matt DeVillier
commit 835b63980d
1 changed files with 6 additions and 8 deletions
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14
src/soc/intel/pantherlake/meminit.c
View file

@ -35,18 +35,16 @@ static const struct soc_mem_cfg soc_mem_cfg[] = {
.num_phys_channels = DDR5_CHANNELS,
.phys_to_mrc_map = {
[0] = 0,
[1] = 1,
[2] = 4,
[3] = 5,
[1] = 4,
},
.md_phy_masks = {
/*
* Physical channels 0 and 1 are populated in case of
* half-populated configurations.
* Only channel 0 is populated in case of half-populated
* configuration.
*/
.half_channel = BIT(0) | BIT(1),
/* In mixed topology, channels 2 and 3 are always memory-down. */
.mixed_topo = BIT(2) | BIT(3),
.half_channel = BIT(0),
/* In mixed topologies, either channel 0 or 1 can be memory-down. */
.mixed_topo = BIT(0) | BIT(1),
},
},
[MEM_TYPE_LP5X] = {